Systemverilog 结构体

Design data often has a variety of types, such as logic, vector, bit. Systemverilog structure can group them together to reduce the declaration redundancy. It is declared with struct . An example is that
struct { int a, b;// 32-bit variables
opcode_t opcode; // user-defined type
logic [23:0] address; // 24-bit variable
bit error;1-bit 2-state var. } Instruction_Word;
A name can be referenced with .

struct { int a, b;// 32-bit variables 
					opcode_t opcode; // user-defined type 
					logic [23:0] address; // 24-bit variable 
					bit error;1-bit 2-state var. } Instruction_Word;

Assigning values to structures:
The member of structure can be initialized with '{}, for example:
instruction_word_t IW = ’{100, 3, 8’hFF, 0};

Packed and unpacked structure:
A structure can be explicitly declared as a packed structure, using the packed keyword. A packed structure can be continious bit and can be treated as a vector:

struct packed { logic valid;
						logic [ 7:0] tag; 
						logic [31:0] data; } data_word;

Passing structures through ports
structure can be declared in port or interface must be defined as user-defined type

package definitions; 
typedef enum {ADD, SUB, MULT, DIV} opcode_t; 
typedef struct { logic [31:0] a, b; 
opcode_t opcode;
 logic [23:0] address; 
 logic error; } instruction_word_t; 
 endpackage 
 module alu (input definitions::instruction_word_t IW, input wire clock); ... 
 endmodule

Pass structure as argument in task or function. e,g,

module processor (...);
 ... 
typedef enum {ADD, SUB, MULT, DIV} opcode_t; 
typedef struct { // typedef is local 
logic [31:0] a, b; 
opcode_t opcode;
 logic [23:0] address; 
 logic error; } instruction_word_t; 
 function alu (input instruction_word_t IW);
  ... 
  endfunction 
  endmodule