VHDL实现优先排队电路

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity paidui is
port(a,b,c:in std_logic;
aout,bout,cout:out std_logic );
end entity paidui;
architecture art of paidui is
signal outs:std_logic_vector(2 downto 0);
begin
outs(2 downto 0)<=“100” when a =‘1’ else
“010” when b =‘1’ else
“001” when c =‘1’ else
“000” ;
aout<=outs(2); bout<=outs(1); cout<=outs(0);
end architecture art;