HLS IP核m_axi接口直接与DDR交互数据

大体步骤同之前写的差不多

https://blog.csdn.net/qq_40268672/article/details/104620907
我的板子型号是xc7z010-clg400-1,可以从xparameters.h头文件中看到，DDR的起始地址为
一共511M，至于为什么少了1M也不清楚，可能有专门的用途，留待以后研究。

CPU端代码

```c
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

/*
 * helloworld.c: simple test application
 *
 * This application configures UART 16550 to baud rate 9600.
 * PS7 UART (Zynq) is not initialized by this application, since
 * bootrom/bsp configures it to baud rate 115200
 *
 * ------------------------------------------------
 * | UART TYPE   BAUD RATE                        |
 * ------------------------------------------------
 *   uartns550   9600
 *   uartlite    Configurable only in HW design
 *   ps7_uart    115200 (configured by bootrom/bsp)
 */

#include 
#include
#include "platform.h"
#include "xil_printf.h"
#include "xmem_test_hw.h"
#include "xmem_test.h"
int main()
{
    init_platform();
    Xil_DCacheDisable();
    int i;
    for(i=0;i<50;i++)
    	Xil_Out32(XPAR_PS7_DDR_0_S_AXI_BASEADDR+i*4,i);
    for(i=0;i<50;i++)
    {
        int rev=Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR+i*4);
        printf("%d\n",rev);
    }
    XMem_test HlsXMem_test;
    XMem_test_Config *ExamplePtr;
    printf("Look Up the device configuration.\n");
    ExamplePtr = XMem_test_LookupConfig(XPAR_MEM_TEST_0_DEVICE_ID);
    if (!ExamplePtr) {
    printf("ERROR: Lookup of accelerator configuration failed.\n\r");
    return XST_FAILURE;
    }
    printf("Initialize the Device\n");
    long status = XMem_test_CfgInitialize(&HlsXMem_test, ExamplePtr);
    if (status != XST_SUCCESS) {
    printf("ERROR: Could not initialize accelerator.\n\r");
    return(-1);
    }
    XMem_test_Set_a(&HlsXMem_test,XPAR_PS7_DDR_0_S_AXI_BASEADDR);
    XMem_test_Start(&HlsXMem_test);
    while (XMem_test_IsDone(&HlsXMem_test) == 0);

    int p=XMem_test_Get_a(&HlsXMem_test);
    printf("%x\n",p);
    for(i=0;i<50;i++){
        	int rev=Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR+4*i);
        	printf("%d\n",rev);
        }
    cleanup_platform();
    return 0;
}

这里注意，因为CPU有Cache，所以为了保证pl端一直读写DDR而不是cache，需要关闭DCache,使用Xil_DCacheDisable()函数。当然这是一种简单粗暴的方法。如果不关闭Cache，会发现PL端IP核运行后，原数据并没有发生变化，关闭DCache后，得到预期结果

DDR和PL之间这种通过AXI总线（突发模式）传输数据的方式，能极大的提高数据吞吐率，而且使用方便。

第二次更新

找到了Cache问题的新方法，如下两个函数
Xil_DCacheFlushRange((u32)sendram,sizeofbuffer)
Xil_DCacheInvalidateRange((u32)recvram,sizeofbuffer)
Cache Flush就是把Cache里的数据流放出去，清空Cache，也就是将Cache的内容推到DDR中去；而Cache Invalidate表示当场宣布Cache里的内容无效，需要从DDR中重新加载，即把数据从DDR中拉到Cache中来,
因此程序可设计如下：
1.向DDR指定的一段空间中写入数据（实际只写入了DCache)
2.调用Xil-DCacheFlushRange()函数
3.启动PL端IP核运行
4.运行结束后调用Xil_DCacheInvalidateRange()函数
5.读取数据
代码如下：

/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

/*
 * helloworld.c: simple test application
 *
 * This application configures UART 16550 to baud rate 9600.
 * PS7 UART (Zynq) is not initialized by this application, since
 * bootrom/bsp configures it to baud rate 115200
 *
 * ------------------------------------------------
 * | UART TYPE   BAUD RATE                        |
 * ------------------------------------------------
 *   uartns550   9600
 *   uartlite    Configurable only in HW design
 *   ps7_uart    115200 (configured by bootrom/bsp)
 */

#include 
#include
#include "platform.h"
#include "xil_printf.h"
#include "xmem_test_hw.h"
#include "xmem_test.h"
int main()
{
    init_platform();
    int i;
    for(i=0;i<50;i++)
    	Xil_Out32(XPAR_PS7_DDR_0_S_AXI_BASEADDR+i*4,i);
    Xil_DCacheFlushRange((u32)XPAR_PS7_DDR_0_S_AXI_BASEADDR,50*sizeof(int));
    for(i=0;i<50;i++)
    {
        int rev=Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR+i*4);
        printf("%d\n",rev);
    }
    XMem_test HlsXMem_test;
    XMem_test_Config *ExamplePtr;
    printf("Look Up the device configuration.\n");
    ExamplePtr = XMem_test_LookupConfig(XPAR_MEM_TEST_0_DEVICE_ID);
    if (!ExamplePtr) {
    printf("ERROR: Lookup of accelerator configuration failed.\n\r");
    return XST_FAILURE;
    }
    printf("Initialize the Device\n");
    long status = XMem_test_CfgInitialize(&HlsXMem_test, ExamplePtr);
    if (status != XST_SUCCESS) {
    printf("ERROR: Could not initialize accelerator.\n\r");
    return(-1);
    }
    XMem_test_Set_a(&HlsXMem_test,XPAR_PS7_DDR_0_S_AXI_BASEADDR);
    XMem_test_Start(&HlsXMem_test);
    while (XMem_test_IsDone(&HlsXMem_test) == 0);

    int p=XMem_test_Get_a(&HlsXMem_test);
    printf("%x\n",p);
    Xil_DCacheInvalidateRange((u32)XPAR_PS7_DDR_0_S_AXI_BASEADDR,sizeof(int)*50);
    for(i=0;i<50;i++){
        	int rev=Xil_In32(XPAR_PS7_DDR_0_S_AXI_BASEADDR+4*i);
        	printf("%d\n",rev);
        }
    cleanup_platform();
    return 0;
}