FPGA中各种分频的verilog 编写

分频这里分为大体偶数和奇数，占空比为50%

用计数来完成分频，每种分频用一个寄存器来计数。

verilog 代码如下：

module div_clk(
					clk,
					reset_n,
					div_clk_pos,
					div_clk_neg,
					div_clk_2_N
					);
input  clk;
input  reset_n;
output reg div_clk_pos;  
output 	  div_clk_neg;
output reg div_clk_2_N;

//pos num 50%
parameter div_constant_pos = 6;

reg [31:0] pos_cnt;
always@(posedge clk or negedge reset_n)
	begin
		if(reset_n == 1'b0)
			begin
				pos_cnt <= 0;
			end
		else if(pos_cnt == div_constant_pos - 1)
			begin
				pos_cnt <= 1'b0;
			end
		else
			begin
				pos_cnt <= pos_cnt + 1'b1;
			end
	end

always@(posedge clk)
	begin
		if(pos_cnt >= 0 && pos_cnt < div_constant_pos>>1) 
			begin
				div_clk_pos <= 0;
			end
		else 
			begin
				div_clk_pos <= 1;
			end
	end

//neg num 50%
parameter div_constant_neg = 7;
reg [31:0] neg_cnt;
reg clk_pos;
reg clk_neg;
always@(posedge clk or negedge reset_n)
	begin
		if(reset_n == 1'b0)
			begin
				neg_cnt <= 0;
			end
		else if(neg_cnt == div_constant_neg - 1)
			begin
				neg_cnt <= 0;
			end
		else
			begin
				neg_cnt <= neg_cnt + 1;
			end
	end
	
always@(posedge clk)
	begin
		if(neg_cnt>=0 && neg_cnt < (div_constant_neg >>1))
			begin
				clk_pos <= 1;
			end
		else
			begin
				clk_pos <= 0;
			end
	end
always@(negedge clk)
	begin
		if(neg_cnt>=0 && neg_cnt < (div_constant_neg >>1))
			begin
				clk_neg <= 1;
			end
		else
			begin
				clk_neg <= 0;
			end
	end
assign div_clk_neg = clk_neg || clk_pos;
	
//(2*2) n 
parameter div_MSB_N = 2;
parameter div_MSB_num = 4;
reg [div_MSB_N-1:0] n_cnt;

always@(posedge clk or negedge reset_n)
	begin
		if(reset_n == 1'b0)
			begin
				n_cnt <= 1'b0;
			end
		else 
			begin
				n_cnt <= n_cnt + 1'b1;
			end
	end
	
always@(posedge clk)
	begin
		if(n_cnt >= 0 && n_cnt < div_MSB_num>>1)
			div_clk_2_N <= 1;
		else
			div_clk_2_N <= 0;
	end
	


endmodule

仿真结果