imx53 时钟dpll分析

DPLL reference clock

There are four DPLL's in i.MX53 project namely:

• DPLL-1 (typical functional frequency 800Mhz)

• DPLL-2 (typical functional frequency 400Mhz)

• DPLL-3 (typical functional frequency 216Mhz)

• DPLL-4 (typical functional frequency 595Mhz)

Each DPLL is controlled by a DPLLC-n interface block. Each DPLLC interface block

uses the output of on chip oscillator (typical frequency is 24Mhz) as DPLL reference

clock.

 

Reset Values for DPLLC

Reset values that are hard coded as DPLLC initialization values are:

DPLL1 - initial value =192Mhz

DPLL2 - initial value = 192Mhz

DPLL3 - initial value = 168Mhz

DPLL4 - initial value = 168Mhz

These frequencies correspond to the reference clock source of on chip oscillator (24

MHz) as the source for DPLL. For different frequencies, a linear ratio should be applied.