verilog代码风格——PN序列产生代码

在编写Verilog代码时注意以下点：

1 、同一个模块中不同变量的赋值放在不同的always块里（这样可以便于程序的调试），一个always块的代码

       尽量不要超过十行。

2、同一个变量的赋值不能放在多个always块中，只能放在同一always块

2、复位信号一定要干净，尽量不要与其他的信号进行逻辑运算

3、利用时钟信号（clk）和复位信号(rst)做触发，尽量避免用中间变量的上升或者下降沿触发

示例代码如下（PN序列的产生）：

//---------------------------------------------------------------------------------------------------

//-- Project name  : DTMB 1.0 IP Development

//-- Filename        : dtmb_pn_gen.v

//-- Called by        : dtmb_pn_gen.v                               

//-- Description    : DTMB fine channle estimation

//-- Moficiation History :

//-------------------------------------------------------------------------------------------

//--     Date           |        By                     |  Version  |  Change Description

//-------------------------------------------------------------------------------------------

//--  2014-07-24 |    Zhenzhen Peng |    0.2    |  Second   Version     

//----------------------------------------------------------------------------------------------

`timescale 1ns/10fs

 

modulepn_module2_m_function

  ( 

    // input

    i_clk_x16g                , // x16 clock, Gated 120.96MHz

    i_rst_n                       , // Negative reset for all EQ

    i_m_intiphase         , // Initial phase

    i_pn_mode              , // 0->255, 1->1023, 2->511, 3->x

    i_pn_length             , // 0->420, 1->595, 2->945, 3->x

    i_module2_start     , // PN start signal

 

    o_pn_gen_en          , // PN seq out enable

    o_pn_gen_start       , // PN start signal

    o_pn_gen_seq         , // PN sequence: 0->+PN , 1->-PN

     o_module2_count    // control the output signal 

  );

//=========================================================

// Parameter

//=========================================================   

parameter    D_W = 12,

                       output_lenght=2048  ; // output data lenght

 //=========================================================

// Interface definition

//=========================================================   

input                     i_clk_x16g            ; // x16 clock, Gated 120.96MHz

input                     i_rst_n                   ;// Negative reset for all EQ

input   [    1 : 0]    i_pn_mode           ;// 0->420, 1->595, 2->945, 3->x

input   [    9 : 0]    i_m_intiphase      ;// the PN initial phase

input                     i_module2_start  ; // pn_module2_m_function module start signal

input   [    9 : 0]    i_pn_length           ;// 0->420, 1->595, 2->945, 3->x

// output

output                 o_pn_gen_start        ; // PN start signal

output                 o_pn_gen_en           ;// PN seq out enable

output  [D_W-1 : 0] o_pn_gen_seq   ;// PN sequence: 0->+PN , 1->-PN

output  [   11 : 0]  o_module2_count  ; // control the output signal 

//=========================================================

// Behavior

//=========================================================  

reg                                    o_pn_gen_start       ;

reg                                    o_pn_gen_en          ; // PN seq out enable

reg signed [D_W-1 : 0] o_pn_gen_seq        ; // PN sequence: 0->+PN , 1->-PN

reg        [   11 : 0]             o_module2_count  ; // control the output signal of o_m_out,o_module2_over

 

reg                      m_flag           ;// m_flag=1, the shifting register is working

reg                      m_out            ; // the output bit value 

reg     [    9 : 0]    m_Init           ; // shifting register

 

// m_flag

always @(posedge i_clk_x16g or negedge i_rst_n)//a clk delay use to delivery the phase

begin                                    

  if(!i_rst_n)  m_flag<=1'b0;

  else if(i_module2_start) m_flag<=1'b1;

  else m_flag<=1'b0;

end

 

// o_module2_count

always @(posedge i_clk_x16gor negedge i_rst_n)

begin

  if(!i_rst_n)  o_module2_count<='b0;

  else if (m_flag )o_module2_count<=o_module2_count+1;

  else o_module2_count<='b0;

end

 

// o_pn_gen_start

always @(posedge i_clk_x16gor negedge i_rst_n)

begin

 if(!i_rst_n)  o_pn_gen_start <=1'b0;

 else if(m_flag) begin

    if(o_module2_count==1)  o_pn_gen_start <=1'b1;

    else o_pn_gen_start <=1'b0;

         end  

end

 

//o_pn_gen_en

always @(posedge i_clk_x16gor negedge i_rst_n)

begin

 if(!i_rst_n)  o_pn_gen_en <=1'b0;

 else if(m_flag) begin

     if(o_module2_count==1)o_pn_gen_en <=1'b1;

          if(o_module2_count==output_lenght+1)o_pn_gen_en <=1'b0;

         end

end

 

//o_pn_gen_seq

always @(posedge i_clk_x16g or negedge i_rst_n)

begin

 if(!i_rst_n) o_pn_gen_seq<='b0;

 else if(o_module2_count)                                       // output_lenght 2048

     if(o_module2_count<=i_pn_length) 

     begin

                  if(m_out==1) o_pn_gen_seq<=-'d362; //BPSK mapper: 1—> -1  0—>1  then QPSK mapper:(sqrt(2)/2 )*(1+i),and(12,2,t)quantitative, so is 362

                                                                                   //the Real data is similar to the imaginary data

                  elseo_pn_gen_seq<='d362;    

          end

         else o_pn_gen_seq<='b0;

end

 

//m_Init

//m_out

always @(posedge i_clk_x16gor negedge i_rst_n)

begin

  if(!i_rst_n)begin

     m_Init<='b0;

           m_out<='b0;

  end 

  else begin//m sequence generator

      if(!m_flag && i_module2_start) m_Init<=i_m_intiphase;

           else if(o_module2_count<=i_pn_length)

             case(i_pn_mode)//0->PN420, 1->PN595, 2->PN945

                            2'b00:  begin //255

                              m_out <=m_Init[7];

                              m_Init<= {m_Init[6:0],m_Init[7]^m_Init[5]^m_Init[4]^m_Init[0]};  

                            end

                            2'b01:  begin//1023

                              m_out <=m_Init[9];

                             m_Init <= {m_Init[8:0],m_Init[9]^m_Init[2]};

                            end

                            2'b10:         begin//511

                               m_out <=m_Init[8];

                               m_Init <= {m_Init[7:0],m_Init[8]^m_Init[7]^m_Init[6]^m_Init[1]};

                            end

             endcase               

    end

end

endmodule               

 

 

PN前一个模块：相位的产生

//----------------------------------------------------------------------
//-- Project name : DTMB 1.0 IP Development
//-- Filename      : dtmb_pn_gen.v
//-- Called by     : dtmb_pn_gen.v  
//-- Author         :                              
//-- Email          :                                   
//-- Description  : DTMB fine channle estimation
//-- Moficiation History :
//----------------------------------------------------------------------
//--     Date    |        By        |  Version  |  Change Description
//----------------------------------------------------------------------
//--  2014-07-14 |    ******     |    0.1    |  Original Version
//--  2014-07-24 |   *******     |    0.2    |  Second Version
//----------------------------------------------------------------------          
//----------------------------------------------------------------------

`timescale 1ns/10fs

module dtmb_pn_phase
  ( 
    // input
    i_clk_x16g      , // x16 clock, Gated 120.96MHz
    i_rst_n         , // Negative reset for all EQ
 i_pn_mode       , // 0->420, 1->595, 2->945, 3->x
    i_frame_index   , // Frame index
    i_pn_gen_start  , // pn_gen module start signal
    i_module2_count ,
 
    // output
    o_m_intiphase   , // PN initial phase
 o_module2_start   // dtmb_pn_seq module enable
  );

//=========================================================
// Interface definition
//=========================================================   
input                  i_clk_x16g       ; // x16 clock, Gated 120.96MHz
input                  i_rst_n          ; // Negative reset for all EQ
input   [    1 : 0]    i_pn_mode        ; // 0->420, 1->595, 2->945, 3->x
input   [    7 : 0]    i_frame_index    ; // Frame index
input                  i_pn_gen_start   ; // dtmb_pn_phase module start signal
input   [   11 : 0]    i_module2_count  ;
// output
output  [    9 : 0]    o_m_intiphase    ; // PN initial phase
output                 o_module2_start  ; // dtmb_pn_seq module enable

//=========================================================
// Parameter
//=========================================================   
parameter    D_W = 12,
             output_lenght=2048         ; // output data lenght
//=========================================================
// Behavior
//=========================================================   
reg                    o_module2_start  ;
reg     [    9 : 0]    o_m_intiphase    ;

reg     [    9 : 0]    m_intiphase_420  ; // PN420 initial phase
reg     [    9 : 0]    m_intiphase_945  ; // PN945 initial phase
reg     [    9 : 0]    m_intiphase_595  ; // PN595 initial phase

reg                    module1_start    ; // dtmb_pn_phase start signal
reg     [   1 : 0]     module1_count    ; // control the output signal of o_m_out,o_module2_over

// module1_count
always @(posedge i_clk_x16g or negedge i_rst_n)
begin
  if(!i_rst_n)  module1_count<=2'b0;
  else if(module1_start) module1_count<=module1_count+1;
  else if(module1_count==2) module1_count<=2'b0;
end

// module1_start
always @(posedge i_clk_x16g or negedge i_rst_n )
begin
 if(!i_rst_n) module1_start<=1'b0;
 else  if(i_pn_gen_start )  module1_start<=1'b1;
 else  if(module1_count==1)  module1_start<=1'b0;
end 

//o_module2_start
always @(posedge i_clk_x16g or negedge i_rst_n)
begin
  if(!i_rst_n)  o_module2_start<=1'b0;
  else if(module1_count==1) o_module2_start<=1'b1;
  else if(i_module2_count==output_lenght) o_module2_start<=1'b0;
end

//o_m_intiphase
always @(posedge i_clk_x16g or negedge i_rst_n)
begin
  if(!i_rst_n)  o_m_intiphase<='b0;
  else
   case(i_pn_mode)//0->PN420, 1->PN595, 2->PN945
  2'b00: o_m_intiphase<=m_intiphase_420;
     
  2'b01: o_m_intiphase<=m_intiphase_595;
  
  2'b10:o_m_intiphase<=m_intiphase_945;
    endcase  
end

//PN420
always @(posedge i_clk_x16g or negedge i_rst_n)
begin
   if(!i_rst_n)
        m_intiphase_420<='b0;
   else if((module1_start)&&(i_pn_mode==2'b00)) //i_pn_mode:0->420 select the PN420 initial phase
   case(i_frame_index)
  8'd000: m_intiphase_420<=10'b0011111001;
  8'd001: m_intiphase_420<=10'b0011110010;
  8'd002: m_intiphase_420<=10'b0011111100;
  8'd003: m_intiphase_420<=10'b0011100101;
  8'd004: m_intiphase_420<=10'b0001111110;
  8'd005: m_intiphase_420<=10'b0011001011;
  8'd006: m_intiphase_420<=10'b0010111111;
  8'd007: m_intiphase_420<=10'b0010010110;
  8'd008: m_intiphase_420<=10'b0011011111;
  8'd009: m_intiphase_420<=10'b0000101100;
  8'd010: m_intiphase_420<=10'b0011101111;
  8'd011: m_intiphase_420<=10'b0001011001;
  8'd012: m_intiphase_420<=10'b0001110111;
  8'd013: m_intiphase_420<=10'b0010110010;
  8'd014: m_intiphase_420<=10'b0000111011;
  8'd015: m_intiphase_420<=10'b0001100101;
  8'd016: m_intiphase_420<=10'b0010011101;
  8'd017: m_intiphase_420<=10'b0011001010;
  8'd018: m_intiphase_420<=10'b0011001110;
  8'd019: m_intiphase_420<=10'b0010010101;
  8'd020: m_intiphase_420<=10'b0001100111;
  8'd021: m_intiphase_420<=10'b0000101011;
  8'd022: m_intiphase_420<=10'b0000110011;
  8'd023: m_intiphase_420<=10'b0001010110;
  8'd024: m_intiphase_420<=10'b0010011001;
  8'd025: m_intiphase_420<=10'b0010101101;
  8'd026: m_intiphase_420<=10'b0011001100;
  8'd027: m_intiphase_420<=10'b0001011011;
  8'd028: m_intiphase_420<=10'b0011100110;
  8'd029: m_intiphase_420<=10'b0010110110;
  8'd030: m_intiphase_420<=10'b0011110011;
  8'd031: m_intiphase_420<=10'b0001101101;
  8'd032: m_intiphase_420<=10'b0001111001;
  8'd033: m_intiphase_420<=10'b0011011010;
  8'd034: m_intiphase_420<=10'b0010111100;
  8'd035: m_intiphase_420<=10'b0010110100;
  8'd036: m_intiphase_420<=10'b0011011110;
  8'd037: m_intiphase_420<=10'b0001101001;
  8'd038: m_intiphase_420<=10'b0001101111;
  8'd039: m_intiphase_420<=10'b0011010010;
  8'd040: m_intiphase_420<=10'b0000110111;
  8'd041: m_intiphase_420<=10'b0010100100;
  8'd042: m_intiphase_420<=10'b0010011011;
  8'd043: m_intiphase_420<=10'b0001001000;
  8'd044: m_intiphase_420<=10'b0001001101;
  8'd045: m_intiphase_420<=10'b0010010000;
  8'd046: m_intiphase_420<=10'b0000100110;
  8'd047: m_intiphase_420<=10'b0000100000;
  8'd048: m_intiphase_420<=10'b0000010011;
  8'd049: m_intiphase_420<=10'b0001000001;
  8'd050: m_intiphase_420<=10'b0000001001;
  8'd051: m_intiphase_420<=10'b0010000011;
  8'd052: m_intiphase_420<=10'b0010000100;
  8'd053: m_intiphase_420<=10'b0000000110;
  8'd054: m_intiphase_420<=10'b0001000010;
  8'd055: m_intiphase_420<=10'b0000001100;
  8'd056: m_intiphase_420<=10'b0000100001;
  8'd057: m_intiphase_420<=10'b0000011000;
  8'd058: m_intiphase_420<=10'b0000010000;
  8'd059: m_intiphase_420<=10'b0000110001;
  8'd060: m_intiphase_420<=10'b0000001000;
  8'd061: m_intiphase_420<=10'b0001100011;
  8'd062: m_intiphase_420<=10'b0000000100;
  8'd063: m_intiphase_420<=10'b0011000110;
  8'd064: m_intiphase_420<=10'b0000000010;
  8'd065: m_intiphase_420<=10'b0010001101;
  8'd066: m_intiphase_420<=10'b0010000001;
  8'd067: m_intiphase_420<=10'b0000011010;
  8'd068: m_intiphase_420<=10'b0011000000;
  8'd069: m_intiphase_420<=10'b0000110101;
  8'd070: m_intiphase_420<=10'b0011100000;
  8'd071: m_intiphase_420<=10'b0001101011;
  8'd072: m_intiphase_420<=10'b0001110000;
  8'd073: m_intiphase_420<=10'b0011010110;
  8'd074: m_intiphase_420<=10'b0000111000;
  8'd075: m_intiphase_420<=10'b0010101100;
  8'd076: m_intiphase_420<=10'b0010011100;
  8'd077: m_intiphase_420<=10'b0001011000;
  8'd078: m_intiphase_420<=10'b0001001110;
  8'd079: m_intiphase_420<=10'b0010110001;
  8'd080: m_intiphase_420<=10'b0000100111;
  8'd081: m_intiphase_420<=10'b0001100010;
  8'd082: m_intiphase_420<=10'b0010010011;
  8'd083: m_intiphase_420<=10'b0011000101;
  8'd084: m_intiphase_420<=10'b0001001001;
  8'd085: m_intiphase_420<=10'b0010001010;
  8'd086: m_intiphase_420<=10'b0000100100;
  8'd087: m_intiphase_420<=10'b0000010101;
  8'd088: m_intiphase_420<=10'b0010010010;
  8'd089: m_intiphase_420<=10'b0000101010;
  8'd090: m_intiphase_420<=10'b0011001001;
  8'd091: m_intiphase_420<=10'b0001010101;
  8'd092: m_intiphase_420<=10'b0001100100;
  8'd093: m_intiphase_420<=10'b0010101010;
  8'd094: m_intiphase_420<=10'b0000110010;
  8'd095: m_intiphase_420<=10'b0001010100;
  8'd096: m_intiphase_420<=10'b0000011001;
  8'd097: m_intiphase_420<=10'b0010101001;
  8'd098: m_intiphase_420<=10'b0010001100;
  8'd099: m_intiphase_420<=10'b0001010011;
  8'd100: m_intiphase_420<=10'b0001000110;
  8'd101: m_intiphase_420<=10'b0010100110;
  8'd102: m_intiphase_420<=10'b0000100011;
  8'd103: m_intiphase_420<=10'b0001001100;
  8'd104: m_intiphase_420<=10'b0010010001;
  8'd105: m_intiphase_420<=10'b0010011000;
  8'd106: m_intiphase_420<=10'b0011001000;
  8'd107: m_intiphase_420<=10'b0000110000;
  8'd108: m_intiphase_420<=10'b0011100100;
  8'd109: m_intiphase_420<=10'b0001100000;
  8'd110: m_intiphase_420<=10'b0001110010;
  8'd111: m_intiphase_420<=10'b0011000001;
  8'd112: m_intiphase_420<=10'b0010111001;
  8'd113: m_intiphase_420<=10'b0011000001;
  8'd114: m_intiphase_420<=10'b0001110010;
  8'd115: m_intiphase_420<=10'b0001100000;
  8'd116: m_intiphase_420<=10'b0011100100;
  8'd117: m_intiphase_420<=10'b0000110000;
  8'd118: m_intiphase_420<=10'b0011001000;
  8'd119: m_intiphase_420<=10'b0010011000;
  8'd120: m_intiphase_420<=10'b0010010001;
  8'd121: m_intiphase_420<=10'b0001001100;
  8'd122: m_intiphase_420<=10'b0000100011;
  8'd123: m_intiphase_420<=10'b0010100110;
  8'd124: m_intiphase_420<=10'b0001000110;
  8'd125: m_intiphase_420<=10'b0001010011;
  8'd126: m_intiphase_420<=10'b0010001100;
  8'd127: m_intiphase_420<=10'b0010101001;
  8'd128: m_intiphase_420<=10'b0000011001;
  8'd129: m_intiphase_420<=10'b0001010100;
  8'd130: m_intiphase_420<=10'b0000110010;
  8'd131: m_intiphase_420<=10'b0010101010;
  8'd132: m_intiphase_420<=10'b0001100100;
  8'd133: m_intiphase_420<=10'b0001010101;
  8'd134: m_intiphase_420<=10'b0011001001;
  8'd135: m_intiphase_420<=10'b0000101010;
  8'd136: m_intiphase_420<=10'b0010010010;
  8'd137: m_intiphase_420<=10'b0000010101;
  8'd138: m_intiphase_420<=10'b0000100100;
  8'd139: m_intiphase_420<=10'b0010001010;
  8'd140: m_intiphase_420<=10'b0001001001;
  8'd141: m_intiphase_420<=10'b0011000101;
  8'd142: m_intiphase_420<=10'b0010010011;
  8'd143: m_intiphase_420<=10'b0001100010;
  8'd144: m_intiphase_420<=10'b0000100111;
  8'd145: m_intiphase_420<=10'b0010110001;
  8'd146: m_intiphase_420<=10'b0001001110;
  8'd147: m_intiphase_420<=10'b0001011000;
  8'd148: m_intiphase_420<=10'b0010011100;
  8'd149: m_intiphase_420<=10'b0010101100;
  8'd150: m_intiphase_420<=10'b0000111000;
  8'd151: m_intiphase_420<=10'b0011010110;
  8'd152: m_intiphase_420<=10'b0001110000;
  8'd153: m_intiphase_420<=10'b0001101011;
  8'd154: m_intiphase_420<=10'b0011100000;
  8'd155: m_intiphase_420<=10'b0000110101;
  8'd156: m_intiphase_420<=10'b0011000000;
  8'd157: m_intiphase_420<=10'b0000011010;
  8'd158: m_intiphase_420<=10'b0010000001;
  8'd159: m_intiphase_420<=10'b0010001101;
  8'd160: m_intiphase_420<=10'b0000000010;
  8'd161: m_intiphase_420<=10'b0011000110;
  8'd162: m_intiphase_420<=10'b0000000100;
  8'd163: m_intiphase_420<=10'b0001100011;
  8'd164: m_intiphase_420<=10'b0000001000;
  8'd165: m_intiphase_420<=10'b0000110001;
  8'd166: m_intiphase_420<=10'b0000010000;
  8'd167: m_intiphase_420<=10'b0000011000;
  8'd168: m_intiphase_420<=10'b0000100001;
  8'd169: m_intiphase_420<=10'b0000001100;
  8'd170: m_intiphase_420<=10'b0001000010;
  8'd171: m_intiphase_420<=10'b0000000110;
  8'd172: m_intiphase_420<=10'b0010000100;
  8'd173: m_intiphase_420<=10'b0010000011;
  8'd174: m_intiphase_420<=10'b0000001001;
  8'd175: m_intiphase_420<=10'b0001000001;
  8'd176: m_intiphase_420<=10'b0000010011;
  8'd177: m_intiphase_420<=10'b0000100000;
  8'd178: m_intiphase_420<=10'b0000100110;
  8'd179: m_intiphase_420<=10'b0010010000;
  8'd180: m_intiphase_420<=10'b0001001101;
  8'd181: m_intiphase_420<=10'b0001001000;
  8'd182: m_intiphase_420<=10'b0010011011;
  8'd183: m_intiphase_420<=10'b0010100100;
  8'd184: m_intiphase_420<=10'b0000110111;
  8'd185: m_intiphase_420<=10'b0011010010;
  8'd186: m_intiphase_420<=10'b0001101111;
  8'd187: m_intiphase_420<=10'b0001101001;
  8'd188: m_intiphase_420<=10'b0011011110;
  8'd189: m_intiphase_420<=10'b0010110100;
  8'd190: m_intiphase_420<=10'b0010111100;
  8'd191: m_intiphase_420<=10'b0011011010;
  8'd192: m_intiphase_420<=10'b0001111001;
  8'd193: m_intiphase_420<=10'b0001101101;
  8'd194: m_intiphase_420<=10'b0011110011;
  8'd195: m_intiphase_420<=10'b0010110110;
  8'd196: m_intiphase_420<=10'b0011100110;
  8'd197: m_intiphase_420<=10'b0001011011;
  8'd198: m_intiphase_420<=10'b0011001100;
  8'd199: m_intiphase_420<=10'b0010101101;
  8'd200: m_intiphase_420<=10'b0010011001;
  8'd201: m_intiphase_420<=10'b0001010110;
  8'd202: m_intiphase_420<=10'b0000110011;
  8'd203: m_intiphase_420<=10'b0000101011;
  8'd204: m_intiphase_420<=10'b0001100111;
  8'd205: m_intiphase_420<=10'b0010010101;
  8'd206: m_intiphase_420<=10'b0011001110;
  8'd207: m_intiphase_420<=10'b0011001010;
  8'd208: m_intiphase_420<=10'b0010011101;
  8'd209: m_intiphase_420<=10'b0001100101;
  8'd210: m_intiphase_420<=10'b0000111011;
  8'd211: m_intiphase_420<=10'b0010110010;
  8'd212: m_intiphase_420<=10'b0001110111;
  8'd213: m_intiphase_420<=10'b0001011001;
  8'd214: m_intiphase_420<=10'b0011101111;
  8'd215: m_intiphase_420<=10'b0000101100;
  8'd216: m_intiphase_420<=10'b0011011111;
  8'd217: m_intiphase_420<=10'b0010010110;
  8'd218: m_intiphase_420<=10'b0010111111;
  8'd219: m_intiphase_420<=10'b0011001011;
  8'd220: m_intiphase_420<=10'b0001111110;
  8'd221: m_intiphase_420<=10'b0011100101;
  8'd222: m_intiphase_420<=10'b0011111100;
  8'd223: m_intiphase_420<=10'b0011110010;
  8'd224: m_intiphase_420<=10'b0011111001;

  default:m_intiphase_420<=10'bx;
    endcase
  end

//PN945
always @(posedge i_clk_x16g or negedge i_rst_n)
begin
   if(!i_rst_n)
        m_intiphase_945<='b0;
   else if((module1_start)&&(i_pn_mode==2'b10)) //i_pn_mode:2->945 select the PN945 initial phase
   case(i_frame_index)
  8'd000: m_intiphase_945<=10'b0100000101;
  8'd001: m_intiphase_945<=10'b0000001011;
  8'd002: m_intiphase_945<=10'b0110000010;
  8'd003: m_intiphase_945<=10'b0000010111;
  8'd004: m_intiphase_945<=10'b0011000001;
  8'd005: m_intiphase_945<=10'b0000101111;
  8'd006: m_intiphase_945<=10'b0001100000;
  8'd007: m_intiphase_945<=10'b0001011111;
  8'd008: m_intiphase_945<=10'b0000110000;
  8'd009: m_intiphase_945<=10'b0010111110;
  8'd010: m_intiphase_945<=10'b0000011000;
  8'd011: m_intiphase_945<=10'b0101111100;
  8'd012: m_intiphase_945<=10'b0000001100;
  8'd013: m_intiphase_945<=10'b0011111000;
  8'd014: m_intiphase_945<=10'b0100000110;
  8'd015: m_intiphase_945<=10'b0111110000;
  8'd016: m_intiphase_945<=10'b0010000011;
  8'd017: m_intiphase_945<=10'b0111100001;
  8'd018: m_intiphase_945<=10'b0001000001;
  8'd019: m_intiphase_945<=10'b0111000011;
  8'd020: m_intiphase_945<=10'b0100100000;
  8'd021: m_intiphase_945<=10'b0110000110;
  8'd022: m_intiphase_945<=10'b0110010000;
  8'd023: m_intiphase_945<=10'b0100001101;
  8'd024: m_intiphase_945<=10'b0011001000;
  8'd025: m_intiphase_945<=10'b0000011011;
  8'd026: m_intiphase_945<=10'b0101100100;
  8'd027: m_intiphase_945<=10'b0000110111;
  8'd028: m_intiphase_945<=10'b0010110010;
  8'd029: m_intiphase_945<=10'b0001101111;
  8'd030: m_intiphase_945<=10'b0101011001;
  8'd031: m_intiphase_945<=10'b0011011110;
  8'd032: m_intiphase_945<=10'b0010101100;
  8'd033: m_intiphase_945<=10'b0110111101;
  8'd034: m_intiphase_945<=10'b0001010110;
  8'd035: m_intiphase_945<=10'b0101111010;
  8'd036: m_intiphase_945<=10'b0100101011;
  8'd037: m_intiphase_945<=10'b0011110101;
  8'd038: m_intiphase_945<=10'b0010010101;
  8'd039: m_intiphase_945<=10'b0111101010;
  8'd040: m_intiphase_945<=10'b0101001010;
  8'd041: m_intiphase_945<=10'b0111010100;
  8'd042: m_intiphase_945<=10'b0110100101;
  8'd043: m_intiphase_945<=10'b0110101001;
  8'd044: m_intiphase_945<=10'b0011010010;
  8'd045: m_intiphase_945<=10'b0101010010;
  8'd046: m_intiphase_945<=10'b0101101001;
  8'd047: m_intiphase_945<=10'b0010100101;
  8'd048: m_intiphase_945<=10'b0010110100;
  8'd049: m_intiphase_945<=10'b0101001011;
  8'd050: m_intiphase_945<=10'b0001011010;
  8'd051: m_intiphase_945<=10'b0010010111;
  8'd052: m_intiphase_945<=10'b0000101101;
  8'd053: m_intiphase_945<=10'b0100101110;
  8'd054: m_intiphase_945<=10'b0000010110;
  8'd055: m_intiphase_945<=10'b0001011100;
  8'd056: m_intiphase_945<=10'b0100001011;
  8'd057: m_intiphase_945<=10'b0010111001;
  8'd058: m_intiphase_945<=10'b0010000101;
  8'd059: m_intiphase_945<=10'b0101110011;
  8'd060: m_intiphase_945<=10'b0101000010;
  8'd061: m_intiphase_945<=10'b0011100111;
  8'd062: m_intiphase_945<=10'b0110100001;
  8'd063: m_intiphase_945<=10'b0111001111;
  8'd064: m_intiphase_945<=10'b0111010000;
  8'd065: m_intiphase_945<=10'b0110011110;
  8'd066: m_intiphase_945<=10'b0011101000;
  8'd067: m_intiphase_945<=10'b0100111101;
  8'd068: m_intiphase_945<=10'b0101110100;
  8'd069: m_intiphase_945<=10'b0001111011;
  8'd070: m_intiphase_945<=10'b0010111010;
  8'd071: m_intiphase_945<=10'b0011110110;
  8'd072: m_intiphase_945<=10'b0101011101;
  8'd073: m_intiphase_945<=10'b0111101101;
  8'd074: m_intiphase_945<=10'b0110101110;
  8'd075: m_intiphase_945<=10'b0111011011;
  8'd076: m_intiphase_945<=10'b0111010111;
  8'd077: m_intiphase_945<=10'b0110110110;
  8'd078: m_intiphase_945<=10'b0011101011;
  8'd079: m_intiphase_945<=10'b0101101101;
  8'd080: m_intiphase_945<=10'b0001110101;
  8'd081: m_intiphase_945<=10'b0011011010;
  8'd082: m_intiphase_945<=10'b0000111010;
  8'd083: m_intiphase_945<=10'b0110110101;
  8'd084: m_intiphase_945<=10'b0000011101;
  8'd085: m_intiphase_945<=10'b0101101010;
  8'd086: m_intiphase_945<=10'b0000001110;
  8'd087: m_intiphase_945<=10'b0011010101;
  8'd088: m_intiphase_945<=10'b0100000111;
  8'd089: m_intiphase_945<=10'b0110101010;
  8'd090: m_intiphase_945<=10'b0110000011;
  8'd091: m_intiphase_945<=10'b0101010101;
  8'd092: m_intiphase_945<=10'b0111000001;
  8'd093: m_intiphase_945<=10'b0010101010;
  8'd094: m_intiphase_945<=10'b0111100000;
  8'd095: m_intiphase_945<=10'b0101010100;
  8'd096: m_intiphase_945<=10'b0011110000;
  8'd097: m_intiphase_945<=10'b0010101000;
  8'd098: m_intiphase_945<=10'b0101111000;
  8'd099: m_intiphase_945<=10'b0101010001;
  8'd100: m_intiphase_945<=10'b0110111100;
  8'd101: m_intiphase_945<=10'b0101010001;
  8'd102: m_intiphase_945<=10'b0101111000;
  8'd103: m_intiphase_945<=10'b0010101000;
  8'd104: m_intiphase_945<=10'b0011110000;
  8'd105: m_intiphase_945<=10'b0101010100;
  8'd106: m_intiphase_945<=10'b0111100000;
  8'd107: m_intiphase_945<=10'b0010101010;
  8'd108: m_intiphase_945<=10'b0111000001;
  8'd109: m_intiphase_945<=10'b0101010101;
  8'd110: m_intiphase_945<=10'b0110000011;
  8'd111: m_intiphase_945<=10'b0110101010;
  8'd112: m_intiphase_945<=10'b0100000111;
  8'd113: m_intiphase_945<=10'b0011010101;
  8'd114: m_intiphase_945<=10'b0000001110;
  8'd115: m_intiphase_945<=10'b0101101010;
  8'd116: m_intiphase_945<=10'b0000011101;
  8'd117: m_intiphase_945<=10'b0110110101;
  8'd118: m_intiphase_945<=10'b0000111010;
  8'd119: m_intiphase_945<=10'b0011011010;
  8'd120: m_intiphase_945<=10'b0001110101;
  8'd121: m_intiphase_945<=10'b0101101101;
  8'd122: m_intiphase_945<=10'b0011101011;
  8'd123: m_intiphase_945<=10'b0110110110;
  8'd124: m_intiphase_945<=10'b0111010111;
  8'd125: m_intiphase_945<=10'b0111011011;
  8'd126: m_intiphase_945<=10'b0110101110;
  8'd127: m_intiphase_945<=10'b0111101101;
  8'd128: m_intiphase_945<=10'b0101011101;
  8'd129: m_intiphase_945<=10'b0011110110;
  8'd130: m_intiphase_945<=10'b0010111010;
  8'd131: m_intiphase_945<=10'b0001111011;
  8'd132: m_intiphase_945<=10'b0101110100;
  8'd133: m_intiphase_945<=10'b0100111101;
  8'd134: m_intiphase_945<=10'b0011101000;
  8'd135: m_intiphase_945<=10'b0110011110;
  8'd136: m_intiphase_945<=10'b0111010000;
  8'd137: m_intiphase_945<=10'b0111001111;
  8'd138: m_intiphase_945<=10'b0110100001;
  8'd139: m_intiphase_945<=10'b0011100111;
  8'd140: m_intiphase_945<=10'b0101000010;
  8'd141: m_intiphase_945<=10'b0101110011;
  8'd142: m_intiphase_945<=10'b0010000101;
  8'd143: m_intiphase_945<=10'b0010111001;
  8'd144: m_intiphase_945<=10'b0100001011;
  8'd145: m_intiphase_945<=10'b0001011100;
  8'd146: m_intiphase_945<=10'b0000010110;
  8'd147: m_intiphase_945<=10'b0100101110;
  8'd148: m_intiphase_945<=10'b0000101101;
  8'd149: m_intiphase_945<=10'b0010010111;
  8'd150: m_intiphase_945<=10'b0001011010;
  8'd151: m_intiphase_945<=10'b0101001011;
  8'd152: m_intiphase_945<=10'b0010110100;
  8'd153: m_intiphase_945<=10'b0010100101;
  8'd154: m_intiphase_945<=10'b0101101001;
  8'd155: m_intiphase_945<=10'b0101010010;
  8'd156: m_intiphase_945<=10'b0011010010;
  8'd157: m_intiphase_945<=10'b0110101001;
  8'd158: m_intiphase_945<=10'b0110100101;
  8'd159: m_intiphase_945<=10'b0111010100;
  8'd160: m_intiphase_945<=10'b0101001010;
  8'd161: m_intiphase_945<=10'b0111101010;
  8'd162: m_intiphase_945<=10'b0010010101;
  8'd163: m_intiphase_945<=10'b0011110101;
  8'd164: m_intiphase_945<=10'b0100101011;
  8'd165: m_intiphase_945<=10'b0101111010;
  8'd166: m_intiphase_945<=10'b0001010110;
  8'd167: m_intiphase_945<=10'b0110111101;
  8'd168: m_intiphase_945<=10'b0010101100;
  8'd169: m_intiphase_945<=10'b0011011110;
  8'd170: m_intiphase_945<=10'b0101011001;
  8'd171: m_intiphase_945<=10'b0001101111;
  8'd172: m_intiphase_945<=10'b0010110010;
  8'd173: m_intiphase_945<=10'b0000110111;
  8'd174: m_intiphase_945<=10'b0101100100;
  8'd175: m_intiphase_945<=10'b0000011011;
  8'd176: m_intiphase_945<=10'b0011001000;
  8'd177: m_intiphase_945<=10'b0100001101;
  8'd178: m_intiphase_945<=10'b0110010000;
  8'd179: m_intiphase_945<=10'b0110000110;
  8'd180: m_intiphase_945<=10'b0100100000;
  8'd181: m_intiphase_945<=10'b0111000011;
  8'd182: m_intiphase_945<=10'b0001000001;
  8'd183: m_intiphase_945<=10'b0111100001;
  8'd184: m_intiphase_945<=10'b0010000011;
  8'd185: m_intiphase_945<=10'b0111110000;
  8'd186: m_intiphase_945<=10'b0100000110;
  8'd187: m_intiphase_945<=10'b0011111000;
  8'd188: m_intiphase_945<=10'b0000001100;
  8'd189: m_intiphase_945<=10'b0101111100;
  8'd190: m_intiphase_945<=10'b0000011000;
  8'd191: m_intiphase_945<=10'b0010111110;
  8'd192: m_intiphase_945<=10'b0000110000;
  8'd193: m_intiphase_945<=10'b0001011111;
  8'd194: m_intiphase_945<=10'b0001100000;
  8'd195: m_intiphase_945<=10'b0000101111;
  8'd196: m_intiphase_945<=10'b0011000001;
  8'd197: m_intiphase_945<=10'b0000010111;
  8'd198: m_intiphase_945<=10'b0110000010;
  8'd199: m_intiphase_945<=10'b0000001011;
  default:m_intiphase_945<=10'bx;
    endcase
  end

//PN595
always @(posedge i_clk_x16g or negedge i_rst_n)
begin
   if(!i_rst_n)
        m_intiphase_595<='b0;
   else if((module1_start)&&(i_pn_mode==2'b01))  //i_pn_mode:1->595 select the PN595 initial phase  
        m_intiphase_595<=10'b1000000000;
 end 
 
endmodule