数码管显示模块代码实现

数码管显示模块：
3.6.1，数码管显示模块的框图：

3.6.2，数码管显示的 VerilogHDL 源代码：
module display (clk_1,lch,reset,jishi,fee,hex0,hex1,hex2,hex4,hex5,hex6,hex7);
input clk_1,lch,jishi,fee,reset;
output hex0,hex1,hex2, hex4, hex5, hex6, hex7;
wire reset;
wire [7:0] lch;
wire [7:0] jishi;
wire [13:0] fee;
reg [6:0] hex0,hex1,hex2,hex4,hex5,hex6,hex7;
always@(posedge clk_1,negedge reset)
begin
if(!reset)
begin
hex6[6:0]=7’b1000000;
hex7[6:0]=7’b1000000;
hex4[6:0]=7’b1000000;
hex5[6:0]=7’b1000000;
hex0[6:0]=7’b1000000;
hex1[6:0]=7’b1000000;
hex2[6:0]=7’b1000000;
end
case(lch[3:0])
4’b0000:hex6[6:0]=7’b1000000;
4’b0001:hex6[6:0]=7’b1111001;
4’b0010:hex6[6:0]=7’b0100100;
4’b0011:hex6[6:0]=7’b0110000;
4’b0100:hex6[6:0]=7’b0011001;
4’b0101:hex6[6:0]=7’b0010010;
4’b0110:hex6[6:0]=7’b0000010;
4’b0111:hex6[6:0]=7’b1111000;
4’b1000:hex6[6:0]=7’b0000000;
4’b1001:hex6[6:0]=7’b0010000;
default:hex6[6:0]=7’b1000000;
endcase
case(lch[7:4])
4’b0000:hex7[6:0]=7’b1000000;
4’b0001:hex7[6:0]=7’b1111001;
4’b0010:hex7[6:0]=7’b0100100;
4’b0011:hex7[6:0]=7’b0110000;
4’b0100:hex7[6:0]=7’b0011001;
4’b0101:hex7[6:0]=7’b0010010;
4’b0110:hex7[6:0]=7’b0000010;
4’b0111:hex7[6:0]=7’b1111000;
4’b1000:hex7[6:0]=7’b0000000;
4’b1001:hex7[6:0]=7’b0010000;
default:hex7[6:0]=7’b1000000;
endcase
case(jishi[3:0])
4’b0000:hex4[6:0]=7’b1000000;
4’b0001:hex4[6:0]=7’b1111001;
4’b0010:hex4[6:0]=7’b0100100;
4’b0011:hex4[6:0]=7’b0110000;
4’b0100:hex4[6:0]=7’b0011001;
4’b0101:hex4[6:0]=7’b0010010;
4’b0110:hex4[6:0]=7’b0000010;
4’b0111:hex4[6:0]=7’b1111000;
4’b1000:hex4[6:0]=7’b0000000;
4’b1001:hex4[6:0]=7’b0010000;
default:hex4[6:0]=7’b1000000;
endcase
case(jishi[7:4])
4’b0000:hex5[6:0]=7’b1000000;
4’b0001:hex5[6:0]=7’b1111001;
4’b0010:hex5[6:0]=7’b0100100;
4’b0011:hex5[6:0]=7’b0110000;
4’b0100:hex5[6:0]=7’b0011001;
4’b0101:hex5[6:0]=7’b0010010;
4’b0110:hex5[6:0]=7’b0000010;
4’b0111:hex5[6:0]=7’b1111000;
4’b1000:hex5[6:0]=7’b0000000;
4’b1001:hex5[6:0]=7’b0010000;
default:hex5[6:0]=7’b1000000;
endcase
case(fee[3:0])
4’b0000:hex0[6:0]=7’b1000000;
4’b0001:hex0[6:0]=7’b1111001;
4’b0010:hex0[6:0]=7’b0100100;
4’b0011:hex0[6:0]=7’b0110000;
4’b0100:hex0[6:0]=7’b0011001;
4’b0101:hex0[6:0]=7’b0010010;
4’b0110:hex0[6:0]=7’b0000010;
4’b0111:hex0[6:0]=7’b1111000;
4’b1000:hex0[6:0]=7’b0000000;
4’b1001:hex0[6:0]=7’b0010000;
default:hex0[6:0]=7’b1000000;
endcase
case(fee[8:5])
4’b0000:hex1[6:0]=7’b1000000;
4’b0001:hex1[6:0]=7’b1111001;
4’b0010:hex1[6:0]=7’b0100100;
4’b0011:hex1[6:0]=7’b0110000;
4’b0100:hex1[6:0]=7’b0011001;
4’b0101:hex1[6:0]=7’b0010010;
4’b0110:hex1[6:0]=7’b0000010;
4’b0111:hex1[6:0]=7’b1111000;
4’b1000:hex1[6:0]=7’b0000000;
4’b1001:hex1[6:0]=7’b0010000;
default:hex1[6:0]=7’b1000000;
endcase
case(fee[13:10])
4’b0000:hex2[6:0]=7’b1000000;
4’b0001:hex2[6:0]=7’b1111001;
4’b0010:hex2[6:0]=7’b0100100;
4’b0011:hex2[6:0]=7’b0110000;
4’b0100:hex2[6:0]=7’b0011001;
4’b0101:hex2[6:0]=7’b0010010;
4’b0110:hex2[6:0]=7’b0000010;
4’b0111:hex2[6:0]=7’b1111000;
4’b1000:hex2[6:0]=7’b0000000;
4’b1001:hex2[6:0]=7’b0010000;
default:hex2[6:0]=7’b1000000;
endcas e
end
endmodule

3.7，顶层模块：
各模块设计仿真实现后，可分别创建成元件符号。顶层就是将各分模块用 Verilog HDL 语言或者是图形方法连接起来，便可实现系统电路。
3.7.1，顶层模块的 VerilogHDL 源代码：
module PIS_QQ_LX(reset,start,clk,hex0,hex1,hex2,hex4,hex5,hex6,hex7,clk_1);
input reset,start,clk;
output hex0,hex1,hex2,hex4,hex5,hex6,hex7,clk_1;
wire reset,start,clk;
wire [6:0] hex0,hex1,hex2,hex4,hex5,hex6,hex7;
wire clk_1;
wire [7:0] lch,jishi,jishi_1;
wire [13:0] fee;
fenpin QQ1 (.clk(clk), .reset(reset),.clk_1(clk_1)) ;
licheng QQ2 (.clk_1(clk_1), .reset(reset), .start(start), .lch(lch));
js QQ5 (.clk_1(clk_1), .reset(reset), .start(start), .jishi(jishi),.jishi_1(jishi_1));
jf QQ3 (.lch(lch), .jishi_1(jishi_1),.fee(fee));
display QQ4 (.reset(reset),.jishi(jishi), .clk_1(clk_1),.lch(lch), .fee(fee),.hex0(hex0), .hex1(hex1), .hex2(hex2),.hex4(hex4),.hex5(hex5), .hex6(hex6),.hex7(hex7));

endmodule