Introducing a new high-level synthesis tool called HercuLeS

One of the great things regarding my being the editor of Programmable Logic Designline is that I get to hear about all sorts of cool things. Just a couple of days ago, for example, I received an email from Dr. Nikolaos Kavvadias in Greece describing a new High Level Synthesis (HLS) tool called HercuLeS that he’s been working on.

The initial description was so interesting that we arranged a Skype call (isn’t the Internet wonderful?) where Nikolaos explained things in more depth. During our conversation, Nikolaos mentioned that he was very interested in receiving feedback about HercuLeS from experts and users in the field. I replied that he wouldn’t find a more expert group than the readers of EE Times – especially the members of Programmable Logic Designline and EDA Designline .

Based on this, I suggested that Nikolaos penned a few words describing what HercuLeS is and what it does, and also explaining the sort of feedback he’s looking for. Nikolaos replied as follows:

Introduction
HercuLeS ( www.nkavvadias.com/hercules ) is a new High Level Synthesis (HLS) EDA tool that delivers a refreshing look at the hot topic of high level hardware synthesis. [As an aside, HercuLeS is named after the homonymous constellation and not after the demigod.] HercuLeS allows the user to synthesize high-level programming language descriptions to synthesizable RTL VHDL. Developed over the last two years by Dr. Nikolaos Kavvadias, HercuLeS aims to provide the user with an easy-to-grasp, direct, and seamless experience from algorithmic specification to implementation.

The HercuLeS flow
HercuLeS favors simplicity, clean interfaces, and direct yet minimal interaction with the user. The overall HercuLeS flow is divided into three stages as follows:

1. Translation from GIMPLE dumps to a textual intermediate representation called NAC (N-Address Code). GIMPLE dumps are generated by the gcc (GNU compiler collection), a very popular open-source retargetable compiler. NAC is a lightweight, typed-assembly language used as a textual intermediate  representation. This translation is performed by HercuLeS' gimple2nac tool.
2. Translation from NAC to Graphviz CDFGs (Control-Data Flow Graphs). This is performed by HercuLeS' nac2cdfg tool.
3. Translation from CDFGs to synthesizable RTL VHDL code. This is performed by HercuLeS' cdfg2vhdl tool. The generated code adheres to an extended FSMD (Finite-State Machine with Datapath) model of computation.

     
Given a proper frontend to GIMPLE (or directly to NAC), HercuLeS can support any user-defined programming language specification. For example, HercuLeS supports the synthesis of ANSI C code (certain rules apply) to hardware by using the "gimple2nac" prototype frontend.

HercuLeS has been designed to be small and efficient (about 25k lines of code) and supports:

• ANSI C (via the gimple2nac prototype) or NAC input
• Generation of synthesizable RTL VHDL
• The automatic generation of self-checking VHDL testbenches
• Integer and fixed-point (VHDL-2008) arithmetic of arbitrary lengths
• The Synopsys "de-facto standard" libraries and the official IEEE libraries
• Code spanning across several C functions/NAC procedures
• Synchronous read ROM/RAM memories (mappable to FPGA block RAMs)
• Single-dimensional array function/procedure arguments
• Support of streaming outputs (producing a sample at a time)
• Source variables in input specifications are propagated down to RTL VHDL

Specific strengths of HercuLeS
Many of the current HLS tools are capable and mature offerings, especially in the C-like/C++/SystemC realm. There also exist certain academic tools of varying level of completeness.

Academic efforts usually nail down a specific problem (by performing interesting research) but end up in providing a more-or-less incomplete flow. Since our  early discussions from 2008 (referring to the "Group-of-Three"), we have detected that academic efforts have certain drawbacks, such as unnecessary  complexity, steep learning curves, and counter-intuitive assumptions for the habits of potential users.

Regarding commercial flows, there exist undetected or under-developed sweet spots. A few examples are as follows:

1. Lack of commercial support for the VHDL-2008 fixed-point libraries. By comparison, HercuLeS supports sfixed and ufixed vectors alongside the required fixed-point operators for performing the necessary arithmetic.
2. In most flows, optimizations are difficult to develop and maintain. They are affected by infrastructure or API changes which undermine their longevity and usability. With HercuLeS, optimizations can be applied either at the NAC or at the CDFG level by interaction with textual representations, via forms of source transformations or graph rewriting, respectively. This keeps them small and maintainable.
3. HercuLeS uses a purely graph-based backend. The resulting RTL VHDL code is generated solely based on graph representations of the input information. This is a much stronger approach than to resort in users following specific "code templates" in order to get things done by the backend.
4. There exist users, groups and businesses using something different that C++/SystemC coding. For example, we see that the adoption of Python and Go is rapidly increasing, but these users are not offered a clear and easy path to hardware. It should be noted that serious Python and Go frontends to GIMPLE start to be usable. GCC GIMPLE might be the right key to "unlock" programming environments and mentalities that are inaccessible to much bigger players of the HLS/ESL field.

A web-based interface is underway
A web interface will be set up for HercuLeS, scheduled for October 2011. Free access to the web interface (possibly with a limitation on the number of lines of source code) will remain available even after product commercialization as discussed below.

Roadmap
The current product roadmap for HercuLeS is as follows:

• Q3/2011: End of first development cycle. Obtain early user feedback.
• Q4/2011: Access to the web interface; algebraic optimizations.
• Q1/2012: Aggressive optimizer using operation chaining; more optimizations.
• Q2/2012: First integration of black box functions; extended GIMPLE support.
• Q3/2012: End of second development cycle.

The commercialization of HercuLeS
We are currently in the process of founding a company to commercialize HercuLeS technology. A group of three people is involved comprising Dr. Kavvadias as the developer of HercuLeS, a programmer cofounder, and a technical manager cofounder with experience in the field of system synthesis.

Pricing
A highly-competitive pricing scheme will be determined and announced prior to October 2011. One potential scheme would be unlimited access to the web interface for a fee.  Another possibility is a licensed binary release with three years of free updates.

Early user feedback requested
Anyone who is interested in the HercuLeS way of performing high-level synthesis is welcome to contribute with his/her comments, bug reports, and criticism.

Two self-contained packages with examples are available for anyone to evaluate the results generated by HercuLeS. These packages are as follows:

The file www.nkavvadias.com/hercules/nac-examples.zip provides a set of four examples illustrating a NAC-to-VHDL flow.

The file www.nkavvadias.com/hercules/ansic-examples.zip provides test cases from ANSI C to RTL VHDL.

These examples are very easy to use; just unzip the archive, change directory to one of the examples (e.g. fibo) and run ./fibo.sh from a Linux or Cygwin command line. In order to use the packages you will need the GHDL simulator  (http://ghdl.free.fr), which is available for both Linux and Windows. Also, standard Unix tools (make, bash) are required to run the simulation from the provided shell scripts.

Please let me know about anything that comes up in the process – comments, inquiries, complaints, and suggestions.