Verilog HDL 锁存器实现

异步高电平有效

module mm_latch
(
	input C,S,		// Set Q to 1, Clear Q to 0
	output reg Q
);

always @(*)
begin
	if(C)
		Q <= 1'b0;
	else if(S)
		Q <= 1'b1;
	else
		Q <= Q;
end

endmodule

异步低电平有效

module mmc_latch
(
	input S,C,
	output reg Q
);

always @(*)
begin
	if(~C)
		Q <= 1'b0;
	else if(~S)
		Q <= 1'b1;
	else
		Q <= Q;
end

endmodule

同步高电平有效

module mm_latch
(
	input clk,C,S,		// Set Q to 1, Clear Q to 0
	output reg Q
);

always @(posedge clk)
begin
	if(C)
		Q <= 1'b0;
	else if(S)
		Q <= 1'b1;
	else
		Q <= Q;
end

endmodule

同步低电平有效

module mmc_latch
(
	input clk,S,C,
	output reg Q
);

always @(posedge clk)
begin
	if(~C)
		Q <= 1'b0;
	else if(~S)
		Q <= 1'b1;
	else
		Q <= Q;
end

endmodule