HDLbits答案更新系列4(2 Verilog Language 2.5 More Verilog Features)

目录

2.5 More Verilog Features

2.5.1 Conditional ternary operator(Conditional)

2.5.2 Reduction operators(Reduction)

2.5.3 Reduction: Even wider gates(Gates100)

2.5.4 Combinational for-loop: Vector reversal 2(Vector100r)

2.5.5 Combinational for-loop: 255-bit population count(Popcount255)

2.5.6 Generate for-loop: 100-bit binary adder 2(Adder100i)

2.5.7 Generate for-loop: 100-bit digit BCD adder(Bcdadd100)

结语

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今天更新一个小节内容。

2.5 More Verilog Features

2.5.1 Conditional ternary operator(Conditional)

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

    assign min = ((a < b ? a : b) < c ? 
                  (a < b ? a : b) : c) < d ? 
                 ((a < b ? a : b) < c ? 
                  (a < b ? a : b) : c) : d;  

endmodule

这种写法很不好,不利于阅读,不建议大家使用这种方式,多层次的组合逻辑还是建议使用always。

2.5.2 Reduction operators(Reduction)

module top_module (
    input [7:0] in,
    output parity); 
    
    assign parity = ^ in;

endmodule

按位异或,即将输入的每位两两异或,得到最终结果。

2.5.3 Reduction: Even wider gates(Gates100)

module top_module( 
    input [99:0] in,
    output out_and,
    output out_or,
    output out_xor 
);
    
    assign out_and = & in;
    assign out_or = | in;
    assign out_xor = ^ in;

endmodule

2.5.4 Combinational for-loop: Vector reversal 2(Vector100r)

module top_module( 
    input [99:0] in,
    output [99:0] out
);
    
    integer i;
    always@(*)begin
        for(i = 0; i <= 99; i = i + 1)begin
            out[i] = in[99 - i];
        end
    end
    
    /* 
    //the second way
    generate
        genvar i;
        for(i = 0; i <= 99; i = i + 1)begin:reverse
            assign out[i] = in[99 - i];
        end
    endgenerate
    */

endmodule

这里大家注意,第二种方法在generate中使用for循环的时候,一定要在begin后面起一个名字,如本模块中的reverse。

2.5.5 Combinational for-loop: 255-bit population count(Popcount255)

module top_module( 
    input [254:0] in,
    output reg [7:0] out );
    
    integer i;
    always@(*)begin
        out = 8'd0;
        for(i = 0; i <= 254; i = i + 1)begin
            out = out + in[i];     
        end
    end

endmodule

注意,这里会产生锁存器,做题可以,实际运用需要斟酌呀。

2.5.6 Generate for-loop: 100-bit binary adder 2(Adder100i)

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    generate
        genvar i;
        for(i = 0; i <= 99; i = i + 1)begin:adder
        	if(i == 0)begin
            	assign {cout[0], sum[0]} = a[0] + b[0] + cin;
            end
            else begin
            	assign {cout[i], sum[i]} = a[i] + b[i] + cout[i-1];
            end         
        end
    endgenerate

endmodule

这里相当于行波进位加法器。

2.5.7 Generate for-loop: 100-bit digit BCD adder(Bcdadd100)

module top_module( 
    input [399:0] a, b,
    input cin,
    output cout,
    output [399:0] sum );
    
    wire[99:0]	cout_1;
    
    generate
        genvar i;
        for(i = 0; i <= 99; i = i + 1)begin:adder
            if(i == 0)begin
                bcd_fadd u_bcd_fadd(
                    .a		(a[3:0]		),
                    .b		(b[3:0]		),
                    .cin	(cin		),
                    .sum	(sum[3:0]	),
                    .cout	(cout_1[0]	)
                );
            end
            else begin
                bcd_fadd ui_bcd_fadd(
                    .a		(a[4 * i + 3: 4 * i]	),
                    .b		(b[4 * i + 3: 4 * i]	),
                    .cin	(cout_1[i - 1]          ),
                    .sum	(sum[4 * i + 3: 4 * i]  ),
                    .cout	(cout_1[i]              )
                );
            end
        end
        assign cout = cout_1[99];
    endgenerate
                    
endmodule

结语

这个小节涉及到大量的设计技巧,比如for的运用,在设计中很有用,有时候会简化工作量,希望大家能够掌握,我也在一直巩固。先更新一个小节吧,如果有什么问题或错误,欢迎大家指出来,我第一时间回答改正。

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https://hdlbits.01xz.net/wiki/Main_Page

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