verilog 和systemverilog的Timing Check Tasks

Formal Definition

Timing Check Tasks are for verification of timing properties of designs and for reporting timing violations.

Complete description: Language Reference Manual section § 14.5.

Simplified Syntax

$setup(data_event, reference_event, limit[, notifier]) ;

$skew (reference_event, data_event, limit[,notifier]) ;

$hold (reference_event, data_event, limit[,notifier]) ;

$recovery (reference_event, data_event, limit, [notifier]) ;

$setuphold (reference_event, data_event, setup_limit, hold_limit, [notifier]) ;

$width (reference_event, limit, threshold [,notifier]) ;

$period (reference_event, limit[,notifier]) ;

$nochange (reference_event, data_event, start_edge_offset, end_edge_offset [,notifier]) ;

Description

Timing check tasks are invoked every time critical events occur within given time limits. See the table below with descriptions of all arguments:

Argument	Description	Type
Reference_event	The transition at a control signal that establishes the reference time for tracking timing violations on the data_event	Module input or inout that is scalar or vector net
Data_event	The signal change that initiates the timing check and is monitored for violations.	Module input or inout that is scalar or vector net
Limit	A time limit used to detect timing violations on the data_event	Constant expression or specparam
Threshold	The largest pulse width that is ignored by the timing check $width	Constant expression or specparam
Setup_limit	A time limit used to detect timing violations on the data_event for $setup.	Constant expression or specparam
Hold_limit	A time limit used to detect timing violations on the data_event for $hold.	Constant expression or specparam
Notifier	An optional argument that "notifies" the simulator when a timing violation occurs	Register

 

$setupchecks setup time. When modeling synchronous circuits, flip-flops need time to force a correct value. Data cannot change within the setup time because flip-flops cannot detect the new value. If data changes within a given time limit,$setupreports a timing violation. If a data event and reference event occur at the same time there is no violation. The$setupfirst checks timing data then records a new data value. The formula to report a timing violation is as shown below:

(time of reference event) - (time of data event) < limit

Notice that the limit argument has to be a positive number.

$skewchecks the following:

(time of data event) - (time of reference event) > limit

$skewcan be used to check synchronicity of clocks inside a circuit. If different clocks are used in a design and are synchronized,$skewwill report a timing violation when the active edge of one of them occurs outside the time limit allowed for the other clock to occur.

When the data event and the reference event occur at the same time,$skewwill not report a timing violation.

$holdwill report a timing violation if the following formula is true:

(time of data event) - (time of reference event) < limit

$holdsimply checks that data is stable in the specified interval of time after the edge of the clock. In flip-flops, data should remain stable for a given time after the active edge of the clock to allow for propagation of data.

Also, a violation will be reported if the data event and the reference event occur at the same time.

$recoveryresponds when the following formula is true:

(time of data event) - (time of reference event) < limit

The 'reference_event' must be an edge-triggered event: posedge or negedge. A timing violation occurs if the time interval between an edge-triggered reference event and a data event exceeds the 'limit'. If a reference event and data event occur at the same time, a timing violation is reported. If a 'reference_event' argument is specified without edge specification, an error is reported.

$setupholdchecks setup and hold timing violations. This task combines the functionality of$setupand$holdin one task. The following formula has to be applied:

setup_limit + hold_limit > 0

'reference_event' have to be one of the following:

• $holdlower bound event

• $setupupper bound event

'data_event' have to be one of the following:

• $holdupper bound event

• $setuplower bound event

In$widthboth limit and threshold have to be positive numbers. The 'reference_event' must be the edge specification, otherwise an error will be reported. The 'data_event' is not specified directly, but by default means 'reference_event' with opposite edge. A timing violation occurs with the following formula:

threshold < (time of data event) - (time of reference event) < limit

$widthreports when width of the active-edge is too small. In FF case it is very important to ensure that the width of an active-edge is sufficient and FF will work properly.

The$periodchecks that a period of signal is sufficiently long. The reference_event has to be an edge specification. The data_event is not specified directly and by default, is the same as a reference_event. The$periodreports a timing violation when the following formula comes true:

(time of data event) - (time of reference event) < limit

The$nochangechecks if the data signal is stable in an interval of start_edge_offset and end_edge_offset. If the signal has changed, a timing violation is reported. The reference_event argument can be posedge or negedge but the edge control specifiers are disallowed.

Examples

Example 1

modulesetup (data1, data2, q);
inputdata1, data2;
outputq;
and(q, data1, data2);
specify
specparamtsetup = 7, delay = 10 ;
(data1 => q) = 10 ;
$setup(data1,posedgedata2, tsetup);
endspecify
endmodule

Example 2

moduletwo_clocks (clk1, clk2, q);
inputclk1, clk2;
outputq;
specify
  specparamtskew = 7;
  $skew(posedgeclk1,posedgeclk2, tskew);
endspecify
endmodule

Example 3

modulehold (data1, data2, q);
inputdata1, data2;
outputq;
and(q, data1, data2);
specify
specparamthold = 7, delay = 10 ;
(data1 => q) = 10 ;
$hold(posedge data2, data1, thold);
endspecify
endmodule

Example 4

modulerecovery (in1, out1);
inputin1 ;
outputout1 ;
assignout1 = in1?1'b1:1'bz ;
specify
  specparamtrecovery = 10;
  $recovery(posedgein1, out1, trecovery);
endspecify
endmodule

Example 5

modulesetuphold (data1, data2, q);
inputdata1, data2;
outputq;
and(q, data1, data2);
specify
specparamtsetup = 7,
thold = 7,
delay = 10 ;
(data1 => q) = 10 ;
$setuphold(posedge data2, data1, tsetup, thold);
endspecify
endmodule

Example 6

modulewidth (data1, data2, q);
inputdata1, data2;
outputq;
and(q, data1, data2);
specify
specparamtwidth = 10,
delay = 10 ;
(data2 => q) = 10 ;
$width(posedge data2, twidth);
endspecify
endmodule

Example 7

moduledff (clk, q);
inputclk;
outputq;
buf(q, clk);
specify
  specparamtperiod = 100 ;
  $period(posedgeclk, tperiod);
endspecify
endmodule

Example 8

modulenochange (data1, data2, q);
inputdata1, data2;
outputq;
and(q, data1, data2);
specify
specparamtstart = -5,
tend = 5 ;
$nochange(posedge data2, data1, tstart, tend);
endspecify
endmodule

Important Notes

• • All timing check system tasks should be invoked within specify blocks.

https://www.cnblogs.com/zeushuang/archive/2013/01/11/2856276.html