hdlbits_Fsm_hdlc

https://hdlbits.01xz.net/wiki/Fsm_hdlc
有error

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    
    reg [7:0]d;
    always @(posedge clk)
        begin
            if (reset)
                d<=8'b0;
            else
                d<= {in,d[7:1]};
        end
	
    assign disc = (d[6:0]==7'b0111110);
    assign flag = (d==8'b01111110);
    assign err = (d==8'b11111110)|(d==8'b01111111)|(d==8'b11111111);
endmodule