Art of Writing TestBenches (of Verilog HDL)

		Introduction  //简介
		Before you Start
		Example - Counter 计数器举例
		Code for Counter Test Plan Test Cases
		Writing a TestBench //写测试基准程序
		Test Bench Test Bench with Clock generator Test Bench continues... Adding Reset Logic Code of reset logic Adding test case logic   Test Case 1 - Asserting/ De-asserting reset Test Case 2 - Assert/ De-assert enable after reset is applied. Test Case 3 - Assert/De-assert enable and reset randomly. Adding compare Logic

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