计数器0到10（初学FPGA)

 

module counter

(

input clk,

input rst,

output [3:0]cont

);//输入输出

reg [3:0]cont_1;

always@(posedge clk)

begin

if(~rst)

cont_1<=0;

else if(cont_1==4'b10)

cont_1<=0;

else

cont_1<=cont_1+1'b1;

end

assign cont=cont_1;

endcase

测试：

`timescale 1ns/1ns

module counter_tb();

reg clk;

reg rst;

inital

begin

    rst=0;

#100 rst=1;

#1000_000 $stop;

end

initial

begin

clk=0;

end

always #10 clk=~clk;

endmodule