数字跑表———具有暂停、清零功能

数字跑表———具有暂停、清零功能
module paobiao6_14(clk,CLR,K2,PAUSE,data,sm_wei,sm_duan);
input clk;
input CLR;
input K2;
input PAUSE;
output [23:0]data;
output [5:0] sm_wei;//4位数码管的位选信号
output [7:0] sm_duan;//4位数码管共用的段选信号
//----------------------------------------------------------
//分频
integer clk_cnt;
reg clk_500Hz;
always @(posedge clk)
if(clk_cnt==32’d100000)
begin clk_cnt <= 1’b0; clk_500Hz <= ~clk_500Hz;end
else
clk_cnt <= clk_cnt + 1’b1;
//----------------------------------------------------------
//位控制
reg [5:0]wei_ctrl=6’b111110;
always @(posedge clk_500Hz)
wei_ctrl <= {wei_ctrl[4:0],wei_ctrl[5]};
//段控制
reg [3:0]duan_ctrl;
//----------------------------------------------------------
//分频 1Hz
reg clk_1Hz;
integer clk_1Hz_cnt;
always @(posedge clk)

if(clk_1Hz_cnt==32’d250000-1)
begin clk_1Hz_cnt <= 1’b0; clk_1Hz <= ~clk_1Hz;

end
else
clk_1Hz_cnt <= clk_1Hz_cnt + 1’b1;
//----------------------------------------------------------
//循环显示 0-9
//reg [39:0]disp=40’h1234567890;

reg [3:0]ge,shi,bai,qian,wan,shiwan,ge1,shi1,bai1,qian1,wan1,shiwan1;
always @(posedge clk_1Hz)begin
if(!CLR) begin
ge<=4’d0;shi<=4’d0;bai<=4’d0;qian <=4’b0;wan <=4’b0;shiwan <=4’b0;end
else if(!PAUSE)begin
ge1<=ge;shi1<=shi;bai1<=bai;qian1<=qian;wan1<=wan;shiwan1<=shiwan;
end
else if(PAUSE) begin

if (ge < 4'd9) ge <= ge+4'b1;
else
begin ge<=4'd0;
	if (shi < 4'd9)  shi <= shi +4'b1; 
		else 
		begin shi<=4'd0;
		if (bai < 4'd9)  bai <= bai +4'b1; 
			else 
			begin bai<=4'd0;
			 if (qian < 4'd6)  qian <= qian +4'b1; 
					else begin
					qian <=4'b0;
					if (wan < 4'd9)  wan <= wan +4'b1; 
					else begin
						wan <=4'b0;
						if (shiwan < 4'd6)  shiwan <= shiwan  +4'b1; 
						else
						shiwan <=4'b0;
			  end
			 end
			end
		end
	end
end

end
assign data = {shiwan,wan,qian,bai,shi,ge};

always @(posedge clk_1Hz)begin
if(!K2)begin
data[3:0] <= shiwan1;
end
end

/always @(posedge clk)
if(clk_cnt==32’d100000)
begin clk_cnt <= 1’b0; clk_500Hz <= ~clk_500Hz;end
else
clk_cnt <= clk_cnt + 1’b1;
//----------------------------------------------------------
//位控制
reg [3:0]wei_ctrl=4’b1110;
always @(posedge clk_500Hz)
wei_ctrl <= {wei_ctrl[2:0],wei_ctrl[3]};
//段控制
reg [3:0]duan_ctrl;/
always @(wei_ctrl)
case(wei_ctrl)
6’b111110:duan_ctrl=data[3:0];
6’b111101:duan_ctrl=data[7:4];
6’b111011:duan_ctrl=data[11:8];
6’b110111:duan_ctrl=data[15:12];
6’b101111:duan_ctrl=data[19:16];
6’b011111:duan_ctrl=data[23:20];
default:duan_ctrl=4’hf;
endcase
//----------------------------------------------------------
//译码模块
reg [7:0]duan;
always @(duan_ctrl)
case(duan_ctrl)
4’h0:duan=8’b0011_1111;//0
4’h1:duan=8’b0000_0110;//1
4’h2:duan=8’b0101_1011;//2
4’h3:duan=8’b0100_1111;//3
4’h4:duan=8’b0110_0110;//4
4’h5:duan=8’b0110_1101;//5
4’h6:duan=8’b0111_1101;//6
4’h7:duan=8’b0000_0111;//7
4’h8:duan=8’b0111_1111;//8
4’h9:duan=8’b0110_1111;//9
4’ha:duan=8’b0111_0111;//a
4’hb:duan=8’b0111_1100;//b
4’hc:duan=8’b0011_1001;//c
4’hd:duan=8’b0101_1110;//d
4’he:duan=8’b0111_1000;//e
4’hf:duan=8’b0111_0001;//f
4’hf:duan=8’b1111_1111;//不显示
default : duan = 8’b0011_1111;//0
endcase
//----------------------------------------------------------
assign sm_wei =wei_ctrl;
assign sm_duan = ~duan;
endmodule
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https://download.csdn.net/download/weixin_44862868/11242678