Stateflow中转换多个事件触发的状态机HDL生成代码
文件下载：http://download.csdn.net/source/3135551
使用Stateflow设计状态机，可视化调试非常好，便于测试，
生成的效率高，C和HDL 都可以~~~介绍一例给跳沿事件触发
给位电平输入的实例~~~Simulink HDL Coder不支持多事件触发
的FSM生成HDL~~~
如果不在环路中或者环路允许的话，可以在跳沿检测电路前加入一级或多级缓冲，可以
防止亚稳态的发生。
1: // -------------------------------------------------------------
2: //
3: // Module: Chart3
4: // Source Path: state10HDL/state10/Chart3
5: // Hierarchy Level: 1
6: //
7: // -------------------------------------------------------------
8:
9: `timescale 1 ns / 1 ns
10:
11: module Chart3
12: (
13: clk,
14: reset,
15: enb,
16: var,
17: ref,
18: Output_rsvd,
19: locked,
20: lock_indicate
21: );
22:
23:
24: input clk;
25: input reset;
26: input enb;
27: input var;
28: input ref;
29: output signed [7:0] Output_rsvd; // sfix8_En4
30: output locked;
31: output lock_indicate;
32:
33: parameter IN_eight = 0, IN_five = 1, IN_four = 2, IN_nine = 3, IN_one = 4, IN_seven = 5, IN_six = 6, IN_ten = 7, IN_three = 8, IN_two = 9;
34:
35: reg [3:0] is_Chart3; // uint8
36: reg signed [7:0] Output_reg; // sfix8_En4
37: reg locked_reg;
38: reg lock_indicate_reg;
39: reg [3:0] is_Chart3_next; // enumerated type (10 enums)
40: reg signed [7:0] Output_reg_next; // sfix8_En4
41: reg locked_reg_next;
42: reg lock_indicate_reg_next;
43:
44:
45: always @(posedge clk or posedge reset)
46: begin : Chart3_1_process
47: if (reset == 1'b1) beginb0;
48: is_Chart3 <= IN_three;
49: Output_reg <= 0;
50: lock_indicate_reg <= 1'
51: locked_reg <= 1'b0;b0;
52: end
53: else begin
54: if (enb) begin
55: is_Chart3 <= is_Chart3_next;
56: Output_reg <= Output_reg_next;
57: locked_reg <= locked_reg_next;
58: lock_indicate_reg <= lock_indicate_reg_next;
59: end
60: end
61: end
62:
63: always @(is_Chart3, var, ref, Output_reg, locked_reg, lock_indicate_reg) begin
64: is_Chart3_next = is_Chart3;
65: Output_reg_next = Output_reg;
66: locked_reg_next = locked_reg;
67: lock_indicate_reg_next = lock_indicate_reg;
68:
69: case ( is_Chart3)
70: IN_eight :
71: begin
72: if (var) begin
73: is_Chart3_next = IN_eight;
74: Output_reg_next = 80;
75: lock_indicate_reg_next = 1'
76: locked_reg_next = 1'b0;b0;
77: end
78: else if (ref) begin
79: is_Chart3_next = IN_nine;
80: Output_reg_next = 80;
81: locked_reg_next = 1'
82: lock_indicate_reg_next = 1'b0;b1;
83: end
84: end
85: IN_five :
86: begin
87: if (var) begin
88: is_Chart3_next = IN_seven;
89: Output_reg_next = 80;
90: locked_reg_next = 1'
91: lock_indicate_reg_next = 1'b0;b1;
92: end
93: else if (ref) begin
94: is_Chart3_next = IN_six;
95: Output_reg_next = 40;
96: locked_reg_next = 1'
97: lock_indicate_reg_next = 1'b0;b1;
98: end
99: end
100: IN_four :
101: begin
102: if (var) begin
103: is_Chart3_next = IN_five;
104: Output_reg_next = 40;
105: lock_indicate_reg_next = 1'
106: locked_reg_next = 1'b0;b0;
107: end
108: else if (ref) begin
109: is_Chart3_next = IN_three;
110: Output_reg_next = 0;
111: lock_indicate_reg_next = 1'
112: locked_reg_next = 1'b0;b0;
113: end
114: end
115: IN_nine :
116: begin
117: if (var) begin
118: is_Chart3_next = IN_eight;
119: Output_reg_next = 80;
120: lock_indicate_reg_next = 1'
121: locked_reg_next = 1'b0;b1;
122: end
123: else if (ref) begin
124: is_Chart3_next = IN_ten;
125: Output_reg_next = 40;
126: lock_indicate_reg_next = 1'
127: locked_reg_next = 1'b0;b1;
128: end
129: end
130: IN_one :
131: begin
132: if (var) begin
133: is_Chart3_next = IN_seven;
134: Output_reg_next = 80;
135: locked_reg_next = 1'
136: lock_indicate_reg_next = 1'b0;b1;
137: end
138: else if (ref) begin
139: is_Chart3_next = IN_two;
140: Output_reg_next = 0;
141: locked_reg_next = 1'
142: lock_indicate_reg_next = 1'b0;b0;
143: end
144: end
145: IN_seven :
146: begin
147: if (var) begin
148: is_Chart3_next = IN_eight;
149: Output_reg_next = 80;
150: lock_indicate_reg_next = 1'
151: locked_reg_next = 1'b0;b1;
152: end
153: else if (ref) begin
154: is_Chart3_next = IN_six;
155: Output_reg_next = 40;
156: locked_reg_next = 1'
157: lock_indicate_reg_next = 1'b0;b1;
158: end
159: end
160: IN_six :
161: begin
162: if (var) begin
163: is_Chart3_next = IN_seven;
164: Output_reg_next = 80;
165: locked_reg_next = 1'
166: lock_indicate_reg_next = 1'b0;b1;
167: end
168: else if (ref) begin
169: is_Chart3_next = IN_two;
170: Output_reg_next = 0;
171: locked_reg_next = 1'
172: lock_indicate_reg_next = 1'b0;b1;
173: end
174: end
175: IN_ten :
176: begin
177: if (var) begin
178: is_Chart3_next = IN_one;
179: Output_reg_next = 40;
180: locked_reg_next = 1'
181: lock_indicate_reg_next = 1'b0;b1;
182: end
183: else if (ref) begin
184: is_Chart3_next = IN_two;
185: Output_reg_next = 0;
186: locked_reg_next = 1'
187: lock_indicate_reg_next = 1'b0;b0;
188: end
189: end
190: IN_three :
191: begin
192: if (ref) begin
193: is_Chart3_next = IN_three;
194: Output_reg_next = 0;
195: lock_indicate_reg_next = 1'
196: locked_reg_next = 1'b0;b0;
197: end
198: else if (var) begin
199: is_Chart3_next = IN_four;
200: Output_reg_next = 0;
201: lock_indicate_reg_next = 1'
202: locked_reg_next = 1'b0;b1;
203: end
204: end
205: IN_two :
206: begin
207: if (var) begin
208: is_Chart3_next = IN_one;
209: Output_reg_next = 40;
210: locked_reg_next = 1'
211: lock_indicate_reg_next = 1'b0;b0;
212: end
213: else if (ref) begin
214: is_Chart3_next = IN_three;
215: Output_reg_next = 0;
216: lock_indicate_reg_next = 1'
217: locked_reg_next = 1'b0;b0;
218: end
219: end
220: default :
221: begin
222: is_Chart3_next = IN_three;
223: Output_reg_next = 0;
224: lock_indicate_reg_next = 1'
225: locked_reg_next = 1'b0;
226: end
227: endcase
228:
229: end
230:
231: assign Output_rsvd = Output_reg_next;
232: assign locked = locked_reg_next;
233: assign lock_indicate = lock_indicate_reg_next;
234:
235:
236:
237: endmodule // Chart3