[USF-XSim-62] 'elaborate' step failed with error(s).使用vivado进行verilog实验，无法进行仿真，如何解决？

我之前用的vivado2014.3后来用的vivado2015.03,在Windows10操作系统上，想要仿真的时候报如下类似错误

[USF-XSim 62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'D:/lirongcui/learning/cameralink_driver/cameralink_driver.sim/sim_1/behav/elaborate.log' file for more information.
上网上搜了类似错误，都试了行不通。我就根据错误路径打开 elaborate.log查看。里面写的如下

Vivado Simulator 2015.3
Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2015.3/bin/unwrapped/win64.o/xelab.exe -wto 13967f5884014c568322b68bf6471ede --debug typical --relax --mt 2 -L blk_mem_gen_v8_3_0 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot simple_ram_tb_behav xil_defaultlib.simple_ram_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-1374] size mismatch in mixed language port association, vhdl port doutb [D:/lirongcui/learning/cameralink_driver/cameralink_driver.srcs/sources_1/new/simple_dual_ram.v:31]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

里面的error中告诉了我们我的代码第31行有问题，回头找代码发现32位的data_out没写位数。我写的

output ram_data_out；改成了output 【31:0】ram_data_out。这样就可以正常仿真了。之前也遇到了类似的问题，也是这么找到的，之前的是例化的时候没有起名字