【原创】科研训练指导手册(DE2-115_labs_vhdl)-PART6--实验五

5.实验五：时钟与定时器

Part I ：

设计实现一个3位BCD计数器，将其结果显示在7段码显示器HEX2—0上。通过使用DE2-115上的50MHZ时钟信号来驱动计数器，使其每隔一秒进行计数。使用按钮KEY0来作为电路的清零信号。

执行以下步骤：

1创建一个Quartus II 工程，用来在DE2-115上实现预期电路。

2写出预期电路的VHDL代码。

3将VHDL文件包含进工程并编译。

4仿真电路来检测其功能。

5分配引脚。

6重新编译并将其下载进FPGA芯片中。

7通过观测显示器的显示来证实电路是否准确。

Part 1代码：

bcd_counter顶层文件 ：

  1 LIBRARY ieee;
  2 
  3 USE ieee.std_logic_1164.all;
  4 
  5 ENTITY bcd_counter IS
  6 
  7 PORT (
  8 
  9       CLOCK_50  : IN STD_LOGIC;
 10 
 11       KEY       : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
 12 
 13       HEX2      : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
 14 
 15       HEX1      : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
 16 
 17       HEX0      : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
 18 
 19 );
 20 
 21 END bcd_counter;
 22 
 23 ARCHITECTURE trans OF bcd_counter IS
 24 
 25 COMPONENT seg7_lut IS
 26 
 27 PORT (
 28 
 29 oseg      : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
 30 
 31       idig      : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
 32 
 33 );
 34 
 35 END COMPONENT;
 36 
 37 COMPONENT counter10 IS
 38 
 39 PORT (
 40 
 41       en        : IN STD_LOGIC;
 42 
 43       clk       : IN STD_LOGIC;
 44 
 45       rst_n     : IN STD_LOGIC;
 46 
 47       q         : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
 48 
 49 );
 50 
 51 END COMPONENT;
 52 
 53 COMPONENT div IS
 54 
 55 port(
 56 
 57       clk : in std_logic;
 58 
 59       clk1:out std_logic
 60 
 61 );
 62 
 63 END COMPONENT;
 64 
 65 SIGNAL clk_1hz    : STD_LOGIC;
 66 
 67 SIGNAL cnt        : STD_LOGIC_VECTOR(11 DOWNTO 0);
 68 
 69 SIGNAL e2         : STD_LOGIC;
 70 
 71 SIGNAL e3         : STD_LOGIC;
 72 
 73 SIGNAL e1        : STD_LOGIC;
 74 
 75 -- Declare intermediate signals for referenced outputs
 76 
 77 SIGNAL HEX2_xhdl2 : STD_LOGIC_VECTOR(6 DOWNTO 0);
 78 
 79 SIGNAL HEX1_xhdl1 : STD_LOGIC_VECTOR(6 DOWNTO 0);
 80 
 81 SIGNAL HEX0_xhdl0 : STD_LOGIC_VECTOR(6 DOWNTO 0);
 82 
 83 BEGIN
 84 
 85 -- Drive referenced outputs
 86 
 87    HEX2 <= HEX2_xhdl2;
 88 
 89    HEX1 <= HEX1_xhdl1;
 90 
 91    HEX0 <= HEX0_xhdl0;
 92 
 93 e1 <= '1';
 94 
 95    e2 <= cnt(3) AND cnt(0);
 96 
 97    e3 <= e2 AND (cnt(7) AND cnt(4));
 98 
 99 u0 : div
100 
101 PORT MAP (
102 
103          clk1  => clk_1hz,
104 
105          clk  => CLOCK_50
106 
107 );
108 
109    u1 : counter10
110 
111 PORT MAP (
112 
113          en     => e1,
114 
115          clk    => clk_1hz,
116 
117          rst_n  => KEY(0),
118 
119          q      => cnt(3 DOWNTO 0)
120 
121 );
122 
123    u2 : counter10
124 
125 PORT MAP (
126 
127          en     => e2,
128 
129          clk    => clk_1hz,
130 
131          rst_n  => KEY(0),
132 
133          q      => cnt(7 DOWNTO 4)
134 
135 );
136 
137    u3 : counter10
138 
139 PORT MAP (
140 
141          en     => e3,
142 
143          clk    => clk_1hz,
144 
145 rst_n  => KEY(0),
146 
147          q      => cnt(11 DOWNTO 8)
148 
149 );
150 
151    h0 : seg7_lut
152 
153 PORT MAP (
154 
155          oseg  => HEX0_xhdl0,
156 
157          idig  => cnt(3 DOWNTO 0)
158 
159 );
160 
161    h1 : seg7_lut
162 
163 PORT MAP (
164 
165          oseg  => HEX1_xhdl1,
166 
167          idig  => cnt(7 DOWNTO 4)
168 
169 );
170 
171    h2 : seg7_lut
172 
173 PORT MAP (
174 
175          oseg  => HEX2_xhdl2,
176 
177          idig  => cnt(11 DOWNTO 8)
178 
179 );
180 
181 END trans;

 

seg7_lut ：

 1 LIBRARY ieee;
 2 
 3 USE ieee.std_logic_1164.all;
 4 
 5 ENTITY seg7_lut IS
 6 
 7 PORT (
 8 
 9       oseg      : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
10 
11       idig      : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
12 
13 );
14 
15 END seg7_lut;
16 
17 ARCHITECTURE trans OF seg7_lut IS
18 
19 BEGIN
20 
21 PROCESS (idig)
22 
23 BEGIN
24 
25 CASE idig IS
26 
27 WHEN "0001" =>
28 
29             oseg <= "1111001";
30 
31 WHEN "0010" =>
32 
33             oseg <= "0100100";
34 
35 WHEN "0011" =>
36 
37             oseg <= "0110000";
38 
39 WHEN "0100" =>
40 
41             oseg <= "0011001";
42 
43 WHEN "0101" =>
44 
45             oseg <= "0010010";
46 
47 WHEN "0110" =>
48 
49             oseg <= "0000010";
50 
51 WHEN "0111" =>
52 
53             oseg <= "1111000";
54 
55 WHEN "1000" =>
56 
57             oseg <= "0000000";
58 
59 WHEN "1001" =>
60 
61             oseg <= "0011000";
62 
63 WHEN "1010" =>
64 
65             oseg <= "0001000";
66 
67 WHEN "1011" =>
68 
69             oseg <= "0000011";
70 
71 WHEN "1100" =>
72 
73             oseg <= "1000110";
74 
75 WHEN "1101" =>
76 
77             oseg <= "0100001";
78 
79 WHEN "1110" =>
80 
81             oseg <= "0000110";
82 
83 WHEN "1111" =>
84 
85             oseg <= "0001110";
86 
87 WHEN OTHERS =>
88 
89             oseg <= "1000000";
90 
91 END CASE;
92 
93 END PROCESS;
94 
95 END trans;

 

Div：

 1 LIBRARY ieee;
 2 
 3 USE ieee.std_logic_1164.all;
 4 
 5 USE ieee.std_logic_arith.all;
 6 
 7 USE ieee.std_logic_unsigned.all;
 8 
 9 entity  div is
10 
11 port(
12 
13       clk : in std_logic;
14 
15       clk1:out std_logic
16 
17 );
18 
19 end div;
20 
21 architecture mix of  div is
22 
23 signal  count :integer range 0 to 49999999;
24 
25 ----严格来说是从0-49999999，刚好50000000个计数值，正好将50M的时钟分为1Hz的时钟
26 
27 begin
28 
29 clk_div_proc:process(clk)
30 
31 begin
32 
33 if rising_edge(clk) then
34 
35 if count=49999999 then
36 
37          count<=0;
38 
39 else
40 
41          count<=count+1;
42 
43 end if;
44 
45 if count>24999999 then---占空比50%
46 
47           clk1<='1';
48 
49 else clk1<='0';
50 
51 end if;
52 
53 end if;
54 
55 end process clk_div_proc;
56 
57 end mix;

 

counter10 ：

 1 LIBRARY ieee;
 2 
 3 USE ieee.std_logic_1164.all;
 4 
 5 USE ieee.std_logic_unsigned.all;
 6 
 7 ENTITY counter10 IS
 8 
 9 PORT (
10 
11       en        : IN STD_LOGIC;
12 
13       clk       : IN STD_LOGIC;
14 
15       rst_n     : IN STD_LOGIC;
16 
17       q         : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
18 
19 );
20 
21 END counter10;
22 
23 ARCHITECTURE trans OF counter10 IS
24 
25 -- Declare intermediate signals for referenced outputs
26 
27 SIGNAL q_xhdl3    : STD_LOGIC_VECTOR(3 DOWNTO 0);
28 
29 BEGIN
30 
31 -- Drive referenced outputs
32 
33    q <= q_xhdl3;
34 
35 PROCESS (clk, rst_n)
36 
37 BEGIN
38 
39 IF ((NOT(rst_n)) = '1') THEN
40 
41          q_xhdl3 <= "0000";
42 
43 ELSIF (clk'EVENT AND clk = '1') THEN
44 
45 IF ((NOT(en)) = '1') THEN
46 
47             q_xhdl3 <= q_xhdl3;
48 
49 ELSIF (q_xhdl3 = "1001") THEN
50 
51             q_xhdl3 <= "0000";
52 
53 ELSE
54 
55             q_xhdl3 <= q_xhdl3 + "0001";
56 
57 END IF;
58 
59 END IF;
60 
61 END PROCESS;
62 
63 END trans;

 

Part II ：思考题

1)设计实现一个时钟电路，它需要能将小时数（0--23）显示在7段码显示器HEX7—6上，并将分钟数（0--60）显示在HEX5—4上，秒数（0--60）显示在HEX3—2上。使用开关SW15—0来预置小时、分钟。

2)设计并在DE2-115上实现一个反应计时电路：

1该电路通过按下按钮KEY0来置位。

2一段运行时间之后，红色发光二极管LEDR0点亮，同时一个4位BCD计数器开始计数。从电路置位至LEDR0被点亮之间的时间由开关SW7—0来设置。

3被测试反应能力的人需要在看到LEDR0亮起时，尽快按下按钮KEY3来关闭LEDR0，同时停止计数器计数。计数器所记时间即为反应时间，将其显示在HEX2—0上。