基于Verilog的按键控制LED灯

按键控制LED灯

原理图
程序设计

`timescale 1ns / 1ps

module key_led(
input sys_clk,
input sys_rst_n,
input [3:0] key,
output reg [3:0] led
    );
 reg [23:0] cnt;
 reg [1:0] led_control;
 //定义一个计数器 计算led变化的时间
 always@(posedge sys_clk or negedge sys_rst_n)
 begin
    if(!sys_rst_n)
    cnt <= 24'b0;
    else if(cnt < 24'd9)
    cnt <= cnt + 1'b1;
    else
    cnt <= 24'b0;
 end
 //用于设置LED的状态
 always@(posedge sys_clk or negedge sys_rst_n)
 begin
    if(!sys_rst_n)
        led_control <= 2'b00;
    else if(cnt < 24'd9)
        led_control <= led_control + 1'b1;
    else
        led_control <= led_control;
 end 
  
 always@(posedge sys_clk or negedge sys_rst_n)
 begin
    if(!sys_rst_n)
        led <=4'b0;
    else if(key[0] == 0)//当按键0按下时
     begin
        case(led_control)
            2'b00 : led <= 4'b1000;
            2'b01 : led <= 4'b0100;
            2'b10 : led <= 4'b0010;
            2'b11 : led <= 4'b0001;
            default : led <= 4'b0000;
            endcase
     end
    else if(key[1] == 0)//当按键1按下时
          begin
             case(led_control)
                 2'b00 : led <= 4'b0001;
                 2'b01 : led <= 4'b0010;
                 2'b10 : led <= 4'b0100;
                 2'b11 : led <= 4'b1000;
                 default : led <= 4'b0000;
                 endcase
          end
  else if(key[2] == 0)//当按键2按下时
   begin
      case(led_control)
          2'b00 : led <= 4'b1111;
          2'b01 : led <= 4'b0000;
          2'b10 : led <= 4'b1111;
          2'b11 : led <= 4'b0000;
          default : led <= 4'b0000;
          endcase
   end
   else if(key[3] == 0)//当按键3按下时
    led <= 4'b1111;
   else 
    led <= 4'b0000;
 end 
  
endmodule

激励文件

`timescale 1ns / 1ps

module tb_key_led();
reg sys_clk;
reg sys_rst_n;
reg [3:0] key;
wire [3:0] led;

parameter T = 10;
initial
begin
    key = 4'b1111;
    sys_clk = 0;
    sys_rst_n = 0;
#T  sys_rst_n = 1;
    key[0] = 0;
#800 key[0] = 1;
     key[1] = 0;
#800 key[1] = 1;
     key[2] = 0;
#800 key[2] = 1;
     key[3] = 0;
#800 key[3] = 1;
$finish;       
end
always #T sys_clk = ~sys_clk;
key_led u_key_led(
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n),
    .key(key),
    .led(led)
);

endmodule

仿真结果如下