VHDL——4选1数据选择器

1.端口图

2.VHDL语言

2.1case语句

library ieee;
use ieee.std_logic_1164.all;

entity mux4 is
    port(a,b,c,d : in std_logic;
	      s1,s2 : in std_logic;
			z : out std_logic);
end mux4;

architecture behave of mux4 is
signal s : std_logic_vector(1 downto 0);
begin
  s <= s1&s2;
    process(a,b,c,d,s1,s2)
	 begin
	 case s is
	     when "00" => z <= a;
		  when "01" => z <= b;
		  when "10" => z <= c;
		  when "11" => z <= d;
		  when others => z <= 'X';
	 end case;
	 end process;
end behave;
		  

if语句

architecture behave of mux4 is
signal s : std_logic_vector(1 downto 0);
begin
  s <= s1&s2;
    process(a,b,c,d,s1,s2)
	 begin
	      if(s = "00") then z <= a;
		  elsif(s = "01")then z <= b;
		  elsif(s = "10")then z <= c;
		  else z <= d;
	 end if;
	 end process;
end behave;