Verilog 数电实验萤火虫 自己写的不是很好

module lab_6(clk, rst_n, f0, f1, f2, p, sta);
	input wire  clk;
	input wire  rst_n;
	input wire  f0;
	input wire  sta;
	input wire  p;
	
	output wire f1;
	output wire f2;
	
	lab_6_transmission   U2(
			.clk(clk),
			.rst_n(rst_n),
			.f0(f0),
			.f1(f1)
		);
		
endmodule

module lab_6_transmission(clk, rst_n, f0, f1);
	input wire clk;
	input wire rst_n;
	input wire f0;
	output reg f1;
   reg [ 15 : 0 ] time_cnt;
	reg  signal_delay_1;
   reg  signal_delay_2;
	wire pose;
	//依靠这两个常量先将所有时间赋给状态值，S0为低电平，S1为高电平
	localparam  S0 = 1'b0; //状态1：输出低电平，计数器保持为0
	localparam  S1 = 1'b1; //状态2：输出高电平，计数器开始计数 
	reg current_state; //当前状态
	reg next_state;
/********************f0信号上升沿检测********************/
	always @(posedge clk or posedge rst_n) begin
		//当复位信号为高电平时，进行置零复位
		if(rst_n) begin
            signal_delay_1 <= 1'b0;
            signal_delay_2 <= 1'b0; 
        end
        else begin
            signal_delay_1 <= f0;
            signal_delay_2 <= signal_delay_1;
        end
   end
	//当signal_delay_1 = f0 = 1，且上一时刻的signal_delay_2 = f0’ = 0时，
	//上升沿标志位置1,该标志位会保持一个时钟周期
   assign pose = !signal_delay_2 && signal_delay_1;
	/*********************信虫状态寄存器****************************/
	always @ (posedge clk or posedge rst_n) begin
	//当复位信号为高电平时，进行复位为状态S0
	  if(rst_n)
			current_state <= S0;
	  else
			current_state <= next_state;
	end
/*******************在S1状态计数从而产生高电平*****************/

 always @(posedge clk or posedge rst_n) begin
		//当复位信号为高电平时，进行置零复位
		if(rst_n)
			time_cnt <= 0;
		else if(current_state == S1)	//在状态S1时，开始计数
			time_cnt <= time_cnt + 1'b1;
		else
			time_cnt <= 0;
	end/*********************信虫输出信号次态的组合逻辑******************/		
	//状态跳变的条件：
	//S0->S1: 外部信号f0的上升沿触发
	//S1->S0: 计数器到达特定值，此时高电平时间为0.3ms
	always @(*) begin
		case(current_state)
			S0: begin
            if(pose)   //case中嵌套if可行
                next_state = S1;
            else
                next_state = S0;
            end

			S1: begin
			   if(time_cnt > 15000-2)
                next_state = S0;
            else
                next_state = S1;
			end		
			
		endcase
	end

/*********************信虫输出信号输出******************/		
	always @(posedge clk or posedge rst_n)
		//当复位信号为高电平时，进行置零复位
		if(rst_n)    //if中套case
			f1 <= 0;
		else begin
			case(current_state)
			S0: f1 <= 0;
			S1: f1 <= 1;
			endcase
		end
endmodule