硬件实验中期考核实验题目-仅个人记录

Error_Find_clear在我这个文件夹里

实验要求：Error_Find_clear文件夹中有四个含有错误的VHDL语言源码文件及相应的仿真波形文件，修改源代码并完成实验步骤所要求的设计流程，得到仿真结果并加以分析。

实验步骤：①建立工程、②编辑代码、③编译及修改错误、④仿真、⑤根据仿真结果分析模块的功能。

四个给的源文件分别为：

couter12         couter15we         encode_83         ff_d

 源码修改后依次为：

couter12

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity counter12 is
	port 
	(
		clk,clr	: in std_logic;
		q		: out std_logic_vector(3 downto 0);
		co	    : out std_logic
	);
end entity counter12;

architecture rtl of counter12 is
	signal	q_s	: integer range 0 to 15 := 0;
begin
	process (clk)
	begin
		if (clk'event) and (clk='1') then
			if clr = '0' then
				q <= "0000"; co <= '0'; 
			else
				if q_s>=11 then
					q_s <= 0; co <= '1';
				else
					q_s <= q_s + 1; co <= '0';
				end if;
			end if;
		end if;
			q <= conv_std_logic_vector(q_s,4);

	end process;
end rtl;

 couter15we

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter15we is
	port 
	(
		clk,we	: in	std_logic;
		q		: inout	std_logic_vector(3 downto 0);
		co	    : out	std_logic
	);
end entity counter15we;

architecture rtl of counter15we is
	signal	q_s	:	std_logic_vector(3 downto 0);
begin
	process (clk,we)
	begin
	

	
		if (clk'event) and (clk='1') then
			if we = '0' then
				q_s <= q; co <= '0';
			elsif q_s="1110" then
					q_s <= "0000"; co <= '1';
			else
					q_s <= q_s +'1'; co <= '0';
			end if;
		end if;
		
	if we = '1' then
		q <= q_s;
	else
		q <= "ZZZZ";
	end if;
	

	end process;
	
	

end rtl;

encode_83  

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY encode_83 IS
	PORT
	(
		en,i0,i11,i2,i3,i4,i5,i6,i7		: IN	STD_LOGIC;
		d								: OUT	STD_LOGIC_VECTOR(2 DOWNTO 0);
		nul,inv							: OUT	std_LOGIC
	);
END encode_83;

ARCHITECTURE rtl OF encode_83 IS
	SIGNAL	i	: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	i <= i0 & i11 & i2 & i3 & i4 & i5 & i6 & i7;
	PROCESS (en, i)
	BEGIN
		IF en = '0' THEN
			d <= "ZZZ"; nul <= 'Z'; inv <= 'Z';
		ELSE
			CASE i IS
				WHEN "01111111" => d <= "000"; nul <= '0'; inv <= '0';
				WHEN "10111111" => d <= "001"; nul <= '0'; inv <= '0';
				WHEN "11011111" => d <= "010"; nul <= '0'; inv <= '0';
				WHEN "11101111" => d <= "011"; nul <= '0'; inv <= '0';
				WHEN "11110111" => d <= "100"; nul <= '0'; inv <= '0';
				WHEN "11111011" => d <= "101"; nul <= '0'; inv <= '0';
				WHEN "11111101" => d <= "110"; nul <= '0'; inv <= '0';
				WHEN "11111110" => d <= "111"; nul <= '0'; inv <= '0';
				WHEN "11111111" => d <= "111"; nul <= '1'; inv <= '0';
				
				when others => d<="000";nul<='0';inv<='1';
			END CASE;
		END IF;
	END PROCESS;
END rtl;

ff_d

library ieee;
use ieee.std_logic_1164.all;

entity ff_d is
	port 
	(
		clk,set,clr,d	: in std_logic;
		q,nq				: buffer std_logic
	);
end ff_d;

architecture rtl of ff_d is
begin
	process (clk,clr)
	begin
		if clr = '0' then
			q <= '0';
		elsif 
		clk'event and clk='1' then
			if set = '0' then
				q <= '1';
			else
				q <= d;
			end if;
		end if;
	end process;
	nq <= not q;
end rtl;

仿真图关了，后面几个就没存了，直接打开压缩包打开给的仿真输入即可。

错误类型：

"0000 "              '1 ' 

名字里_ _不能连起来成为__ 

 然后就是工程文件名字统一

z->Z

变量类型的选择 与 转换

清零端优先级

couter15we的本意是 把we那一块再扔一个进程中去（我放到了一起

+ 的使用得引用unsigned的那个 库还是包

每个进程中对一个信号进行赋值。（同之前verilog的总结