源码 vivado ram调用与仿真

调用ip

ram_rw.v

module ram_rw (
    //input 
    input clk,
    input rst_n,

    // ram
    // ram input
    input [7:0] ram_rd_data,
    // ram output 
    output ram_en,
    output ram_wea,
    output reg[4:0] ram_addr,
    output reg[7:0] ram_wr_data

);

// reg define
// ram read/write control enable
reg[5:0] rw_cnt;

// main code

// ram enable,
assign ram_en = rst_n;
// ram a read/write enable,1-write;0-read,
assign ram_wea = (rw_cnt <=6'd31 && ram_en == 1'b1)?1'b1:1'b0;
// rw_cnt,count range 0~63,
always @(posedge clk or negedge rst_n)
begin 
    if(rst_n == 1'b0)
        rw_cnt <= 1'b0;
    else if(rw_cnt == 6'd63)
        rw_cnt <= 1'b0;
    else 
        rw_cnt <= rw_cnt + 1'b1;
end

// generate ram write data,
always @(posedge clk or negedge rst_n)
begin
    if(rst_n == 1'b0)
        ram_wr_data <= 1'b0;
    // the ram's depth = 32,
    else if(rw_cnt < 6'd31)
        ram_wr_data <= ram_wr_data + 1'b1;
    else 
        ram_wr_data <= 1'b0;
end

// generate ram address,
always @(posedge clk or negedge rst_n)
begin
    if(rst_n == 1'b0)
        ram_addr <= 1'b0;
    // the ram's depth = 32
    else if(ram_addr == 5'd31)
        ram_addr <= 1'b0;
    else
        ram_addr <=ram_addr + 1'b1;
end
endmodule

 ip_ram.v

module ip_ram(
    input sys_clk,
    input sys_rst_n
);

// wire difine
wire ram_en;
wire ram_wea;
wire [4:0] ram_addr;
wire [7:0] ram_wr_data;
wire [7:0] ram_rd_data;

// main code

// ram_rw instance
ram_rw ram_rw_inst0(
    // input
    .clk(sys_clk),
    .rst_n(sys_rst_n),

    // ram
    // ram input
    .ram_rd_data(ram_rd_data),
    // ram_output
    .ram_en(ram_en),
    .ram_wea(ram_wea),
    .ram_addr(ram_addr),
    .ram_wr_data(ram_wr_data)
);
/*
module ram_rw (
    //input 
    input clk,
    input rst_n,

    // ram
    // ram input
    input [7:0] ram_rd_data,
    // ram output 
    output ram_en,
    output ram_wea,
    output reg[4:0] ram_addr,
    output reg[7:0] ram_wr_data

);
*/

blk_mem_gen_0 blk_mem_gen_0_inst0 (
  .clka(sys_clk),    // input wire clka
  .ena(ram_en),      // input wire ena
  .wea(ram_wea),      // input wire [0 : 0] wea
  .addra(ram_addr),  // input wire [4 : 0] addra
  .dina(ram_wr_data),    // input wire [7 : 0] dina
  .douta(ram_rd_data)  // output wire [7 : 0] douta
);
endmodule

schematic,

 

 

 tb_ip_ram.v

`timescale 1ns/1ns

module tb_ip_ram();

reg clk;
reg rst_n;

always #10 clk = ~clk;

initial begin
    clk = 1'b0;
    rst_n = 1'b0;
    #200
    rst_n = 1'b1;
end

// ip_ram instance
ip_ram ip_ram_inst0(
    .sys_clk(clk),
    .sys_rst_n(rst_n)
);

endmodule

simulation

 just for record