源码 vivado调用FIFO 及仿真

ip core

 

 

 

 

源码

module ip_fifo (
    // input 
    input sys_clk,
    input sys_rst_n
);

// wire define

// fifo's input
wire fifo_wr_en;
wire fifo_rd_en;
wire [7:0] fifo_din;  

// fifo's output 
wire [7:0] fifo_dout;
wire almost_full;
wire almost_empty;
wire fifo_full;
wire fifo_empty;

wire [7:0] fifo_wr_data_count;
wire [7:0] fifo_rd_data_count;

// main code
// fifo_generator_0 instance
fifo_generator_0 fifo_generator_0_inst0 (
  .wr_clk(sys_clk),                // input wire wr_clk
  .rd_clk(sys_clk),                // input wire rd_clk
  .din(fifo_din),                      // input wire [7 : 0] din
  .wr_en(fifo_wr_en),                  // input wire wr_en
  .rd_en(fifo_rd_en),                  // input wire rd_en
  .dout(fifo_dout),                    // output wire [7 : 0] dout
  .full(fifo_full),                    // output wire full
  .almost_full(almost_full),      // output wire almost_full
  .empty(fifo_empty),                  // output wire empty
  .almost_empty(almost_empty),    // output wire almost_empty
  .rd_data_count(fifo_rd_data_count),  // output wire [7 : 0] rd_data_count
  .wr_data_count(fifo_wr_data_count)  // output wire [7 : 0] wr_data_count
);

// write fifo instance
fifo_wr fifo_wr_inst0(
    .clk(sys_clk),
    .rst_n(sys_rst_n),

    .fifo_wr_en(fifo_wr_en),
    .fifo_wr_data(fifo_din),
    .almost_empty(almost_empty),
    .almost_full(almost_full)
);

// read fifo instance
fifo_rd fifo_rd_inst0(
    .clk(sys_clk),
    .rst_n(sys_rst_n),

    .fifo_rd_en(fifo_rd_en),
    .fifo_dout(fifo_dout),
    .almost_empty(almost_empty),
    .almost_full(almost_full)
);
endmodule

 

 

module fifo_wr (
    // input
    input clk,
    input rst_n,

    input almost_empty,
    input almost_full,
    // output
    output reg fifo_wr_en,
    output reg[7:0] fifo_wr_data
);

// reg define
// state machine
reg [1:0] state;
// almost_empty delay 1 tap,&delay 2 taps.
reg almost_empty_d0;
reg almost_empty_syn;
// delay count for almost_empty to ensure the fifo is empty.
reg [3:0] dly_cnt;

// main code
// almost_empty move from read region to write region
always @(posedge clk) begin
    if(!rst_n) begin
        almost_empty_d0 <= 1'b0;
        almost_empty_syn <= 1'b0;
    end
    else begin
        almost_empty_d0 <= almost_empty;
        almost_empty_syn <= almost_empty_d0;
    end  
end  

always @(posedge clk) begin
    if(!rst_n) 
        begin 
            fifo_wr_en <= 1'b0;
            fifo_wr_data <= 8'd0;
            state <= 2'd0;
            dly_cnt <= 4'd0;
        end
    else 
        begin 
            case(state)
                2'b0:
                    begin 
                        if(almost_empty_syn)
                            begin
                                state <= 2'd1; 
                            end
                        else 
                            state <= state;                        
                    end
                2'b1:
                    begin 
                        // delay for 10 taps,
                        // why need 10 taps
                        // because the fifo ip internal status update need delay
                        // we delay 10 taps for updated done.
                        if(dly_cnt == 4'd10)
                            begin
                               dly_cnt <= 4'd0;
                               state <= 2'd2;
                               fifo_wr_en <= 1'b1; 
                            end
                        else
                            dly_cnt <= dly_cnt + 4'd1;
                    end
                2'd2:
                    begin  
                        if(almost_full)
                            begin 
                                fifo_wr_en <= 1'b0;
                                fifo_wr_data <= 8'd0;
                                state <= 2'd0;
                            end
                        else 
                            begin 
                                fifo_wr_en <= 1'b1;
                                fifo_wr_data <= fifo_wr_data + 1'b1;
                            end
                    end
                default:state <= 2'd0;
            endcase
        end

end
endmodule

module fifo_rd (
    // input
    input clk,
    input rst_n,

    input [7:0] fifo_dout,
    input almost_full,
    input almost_empty,
    
    // output 
    output reg fifo_rd_en 
);

// reg define 
// state machine 
reg [1:0] state;  
// almost_full delay 1 tap & 2 taps.
reg almost_full_d0;
reg almost_full_syn;

reg [3:0] dly_cnt;

// main code
always @(posedge clk)
    begin 
        if(!rst_n)
            begin 
                almost_full_d0 <= 1'b0;
                almost_full_syn <= 1'b0;
            end 
        else 
            begin 
                almost_full_d0 <= almost_full;
                almost_full_syn <= almost_full_d0;
            end 
    end 

always @(posedge clk) begin
    if(!rst_n)
        begin 
            fifo_rd_en <= 1'b0;
            state <= 2'd0;
            dly_cnt <= 4'd0;
        end
    else 
        begin 
            case(state)
                2'd0:
                    begin 
                        if(almost_full_syn)
                            state <= 2'd1;
                        else 
                            state <= state;
                    end 
                2'd1:
                    begin 
                        if(dly_cnt == 4'd10)
                            begin 
                                dly_cnt <= 4'd0;
                                state <= 2'd2;
                            end 
                        else 
                            dly_cnt <= dly_cnt + 1'b1;
                    end 
                2'd2:
                    begin 
                        if(almost_empty)
                            begin 
                                fifo_rd_en <= 1'b0;
                                state <= 2'd0;
                            end 
                        else 
                            fifo_rd_en <= 1'b1;
                    end 
                default:state <= 2'd0;
            endcase
        end 
end
endmodule

 

schematic

test bench

 

 

`timescale 1ns/1ns

module tb_ip_fifo();
reg clk;
reg rst_n;

// ip_fifo instance
ip_fifo ip_fifo_inst0(
    .sys_clk(clk),
    .sys_rst_n(rst_n)
);
/*
module ip_fifo (
    // input 
    input sys_clk,
    input sys_rst_n
);
*/ 

// generate the clk 
parameter PERIOD = 20;
always 
    begin 
        clk = 1'b0;
        #(PERIOD/2) clk = 1'b1;
        #(PERIOD/2);
    end 

initial
    begin 
        rst_n = 1'b0;
        #100;
        rst_n = 1'b1;
    end 
endmodule

simulation

 just for record.