OS lab6

Ex1

syscall从time.h中一共只有三个函数一个个试过来也行了

Ex 5
Allocate a region of memory for the transmit descriptor list. Software should insure this memory is aligned on a paragraph (16-byte) boundary.
为传输描述符链分配一个内存区域，并且需要保证这部分内存是16byte内存对齐。
Program the Transmit Descriptor Base Address (TDBAL/TDBAH) register(s) with the address of the region. TDBAL is used for 32-bit addresses and both TDBAL and TDBAH are used for 64-bit addresses. 设置传输描述符基地址寄存器TDBAL/TDBAH(Transmit Descriptor Base Address)，32位只使用TDBAL。
Set the Transmit Descriptor Length (TDLEN) register to the size (in bytes) of the descriptor ring. This register must be 128-byte aligned.
设置传输描述符长度寄存器TDLEN保存描述符环的大小，值必须是128字节对齐
The Transmit Descriptor Head and Tail (TDH/TDT) registers are initialized (by hardware) to 0b after a power-on or a software initiated Ethernet controller reset. Software should write 0b to both these registers to ensure this.
传输描述符头尾寄存器TDH/TDT在加电后被硬件或者以太网控制器初始化为0B，驱动需要确认写入了0B到这两个寄存器。
Initialize the Transmit Control Register (TCTL) for desired operation to include the following: 初始化传输控制寄存器TCTL
• Set the Enable (TCTL.EN) bit to 1b for normal operation. TCTL.EN(enable)置为1b
• Set the Pad Short Packets (TCTL.PSP) bit to 1b. TCTL.PSP(Pad Short Packet)置为1b
• Configure the Collision Threshold (TCTL.CT) to the desired value. Ethernstandard is 10h. This setting only has meaning in half duplex mode.配置碰撞阈值TCTL.CT(Collision Threshold)为以太网标准值10h，半双工模式(half duplex mode)
• Configure the Collision Distance (TCTL.COLD) to its expected value. For full duplex operation, this value should be set to 40h. For gigabit half duplex, this value should be set 配置碰撞距离TCTL.COLD，全双工设置为40h，1000Mb/s半双工的值应该为200h，10/100Mb/s的值应该设置为40h
Program the Transmit IPG (TIPG) register with the following decimal values to get the minimum legal Inter Packet Gap
配置Transmit IPG寄存器，设置为最小合法数据包间隔legal Inter Packet Gap。

Ex 10
Program the Receive Address Register(s) (RAL/RAH) with the desired Ethernet addresses. RAL[0]/RAH[0] should always be used to store the Individual Ethernet MAC address of the Ethernet controller. This can come from the EEPROM or from any other means (for example, on some machines, this comes from the system PROM not the EEPROM on the adapter port).
Initialize the MTA (Multicast Table Array) to 0b. Per software, entries can be added to this table as desired.
Program the Interrupt Mask Set/Read (IMS) register to enable any interrupt the software driver wants to be notified of when the event occurs. Suggested bits include RXT, RXO, RXDMT, RXSEQ, and LSC. There is no immediate reason to enable the transmit interrupts.
If software uses the Receive Descriptor Minimum Threshold Interrupt, the Receive Delay Timer (RDTR) register should be initialized with the desired delay time.
Allocate a region of memory for the receive descriptor list. Software should insure this memory is aligned on a paragraph (16-byte) boundary. Program the Receive Descriptor Base Address(RDBAL/RDBAH) register(s) with the address of the region. RDBAL is used for 32-bit addresses and both RDBAL and RDBAH are used for 64-bit addresses.
Set the Receive Descriptor Length (RDLEN) register to the size (in bytes) of the descriptor ring.
This register must be 128-byte aligned.
The Receive Descriptor Head and Tail registers are initialized (by hardware) to 0b after a power-on or a software-initiated Ethernet controller reset. Receive buffers of appropriate size should be allocated and pointers to these buffers should be stored in the receive descriptor ring. Software initializes the Receive Descriptor Head (RDH) register and Receive Descriptor Tail (RDT) with the appropriate head and tail addresses. Head should point to the first valid receive descriptor in the descriptor ring and tail should point to one descriptor beyond the last valid descriptor in the descriptor ring.
Program the Receive Control (RCTL) register with appropriate values for desired operation to include the following:
• Set the receiver Enable (RCTL.EN) bit to 1b for normal operation. However, it is best to leave
the Ethernet controller receive logic disabled (RCTL.EN = 0b) until after the receive
descriptor ring has been initialized and software is ready to process received packets.
• Set the Long Packet Enable (RCTL.LPE) bit to 1b when processing packets greater than the
standard Ethernet packet size. For example, this bit would be set to 1b when processing Jumbo
Frames.
• Loopback Mode (RCTL.LBM) should be set to 00b for normal operation.
• Configure the Receive Descriptor Minimum Threshold Size (RCTL.RDMTS) bits to the
desired value.
• Configure the Multicast Offset (RCTL.MO) bits to the desired value.
• Set the Broadcast Accept Mode (RCTL.BAM) bit to 1b allowing the hardware to accept broadcast packets.
• Configure the Receive Buffer Size (RCTL.BSIZE) bits to reflect the size of the receive buffers software provides to hardware. Also configure the Buffer Extension Size (RCTL.BSEX) bits if receive buffer needs to be larger than 2048 bytes.
• Set the Strip Ethernet CRC (RCTL.SECRC) bit if the desire is for hardware to strip the CRC prior to DMA-ing the receive packet to host memory.
• For the 82541xx and 82547GI/EI, program the Interrupt Mask Set/Read (IMS) register to enable any interrupt the driver wants to be notified of when the even occurs. Suggested bits include RXT, RXO, RXDMT, RXSEQ, and LSC. There is no immediate reason to enable the transmit interrupts. Plan to optimize interrupts later, including programming the interrupt
moderation registers TIDV, TADV, RADV and IDTR.
• For the 82541xx and 82547GI/EI, if software uses the Receive Descriptor Minimum Threshold Interrupt, the Receive Delay Timer (RDTR) register should be initialized with the desired delay time.