Verilog HDL in one Day Part-II

Control Statements // 控制语句

Wait, what's this? if, else, repeat, while, for, case - it's Verilog that looks exactly like C (and probably whatever other language you're used to program in)! Even though the functionality appears to be the same as in C, Verilog is an HDL, so the descriptions should translate to hardware. This means you've got to be careful when using control statements (otherwise your designs might not be implementable in hardware).

等等，这是些什么？if, else, repeat, while, for, case, 可以看出Verilog HDL 和C看起来一模一样（和其他的你使用的语言）。

尽管这些功能看起来和C语言中的一样，但是Verilog HDL是一种硬件描述语言，因此这些描述能够转化为硬件。这也意味着你要想当的小心当使用控制语句时，否则你的设计可能没法用硬件实现。

		If-else //if-else 分支语句
		If-else statements check a condition to decide whether or not to execute a portion of code. If a condition is satisfied, the code is executed. Else, it runs this other portion of code. if-else 语句检查一个条件来决定是否要执行一个代码块。如果条件满足，代码块被执行，否则，执行代码块的令一个部分。
		1 // begin and end act like curly braces in C/C++. // begin 和end等价于C、C++中{和} 2 if (enable == 1'b1) begin 3 data = 10; // Decimal assigned 4 address = 16'hDEAD; // Hexadecimal 5 wr_enable = 1'b1; // Binary 6 end else begin 7 data = 32'b0; 8 wr_enable = 1'b0; 9 address = address + 1; 10 end You could download file one_day2.v here
		One could use any operator in the condition checking, as in the case of C language. If needed we can have nested if else statements; statements without else are also ok, but they have their own problem, when modeling combinational logic, in case they result in a Latch (this is not always true). 在条件判断中（condition checking）可以使用任何操作符，像C语言中条件判断一样。如果必要的话，我们可以使用嵌套的if-else语句；没有else的语句也是可以的； 但是它们会有自己的问题， 如当使用组合逻辑建模时，会造成闭锁（Latch）现象（不能一直保证正确）。
		Case // case 语句
		Case statements are used where we have one variable which needs to be checked for multiple values. like an address decoder, where the input is an address and it needs to be checked for all the values that it can take. Instead of using multiple nested if-else statements, one for each value we're looking for, we use a single case statement: this is similar to switch statements in languages like C++. 当我们使用一个变量，检查多个值时，使用case 语句；像一个地址解码器，输入一个地址，可以检查所有可能的值。而不是使用多层嵌套的if-else语句；当我们使用一对多的情形，我们只需要使用单个case语句：这和C++中的switch语句非常相似。
		Case statements begin with the reserved word case and end with the reserved word endcase (Verilog does not use brackets to delimit blocks of code). The cases, followed with a colon and the statements you wish executed, are listed within these two delimiters. It's also a good idea to have a default case. Just like with a finite state machine (FSM), if the Verilog machine enters into a non-covered statement, the machine hangs. Defaulting the statement with a return to idle keeps us safe. case 语句以保留字case开头，以保留字endcase（Verilog HDL不使用{}来界定代码块）结束。所有的cases后面紧跟：（colon）接着是我们期待执行的语句放在两个分界符间。使用default case 是一个非常好的注意。 就像在一个有限状态机（FSM， finite state machine)中，如果这个Verilog状态机进入了一种未包含的状态， 状态机将挂掉。default语句,(默认的语句，和路由器中默认路由的功能相似）使状态机处于idle状态，从而使我安全。
		1 case(address) 2 0 : $display ("It is 11:40PM"); 3 1 : $display ("I am feeling sleepy"); 4 2 : $display ("Let me skip this tutorial"); 5 default : $display ("Need to complete"); 6 endcase You could download file one_day3.v here
		Looks like the address value was 3 and so I am still writing this tutorial. 看，像address==3这种情形，输出Need to complete，但是然而我却正在写个这个教程。
		Note: One thing that is common to if-else and case statement is that, if you don't cover all the cases (don't have 'else' in If-else or 'default' in Case), and you are trying to write a combinational statement, the synthesis tool will infer Latch. 注意：在if-else和case语句中如果没有包含所有的情形，并且是组合逻辑电路中， 综合工具出现闭锁，是非常普遍的。
		While // while语句
		A while statement executes the code within it repeatedly if the condition it is assigned to check returns true. While loops are not normally used for models in real life, but they are used in test benches. As with other statement blocks, they are delimited by begin and end. 如果while中条件一直为真，while语句将反复执行其中的代码。在实际的编程中，很少使用 while loop。但是它们使用在测试基准中。 与其他语句块一样，它们也是同begin 和end 进行语句块的界定的。
		1 while (free_time) begin 2 $display ("Continue with webpage development"); 3 end You could download file one_day4.v here
		As long as free_time variable is set, code within the begin and end will be executed. i.e print "Continue with web development". Let's looks at a stranger example, which uses most of Verilog constructs. Well, you heard it right. Verilog has fewer reserved words than VHDL, and in this few, we use even lesser for actual coding. So good of Verilog... so right. 只要free_time被置位，在begin 和end间的代码将一直执行。例如，本例中将一直输出”Continue with web development". 让我们看一个陌生一点的例子，但是使用在大多数的Verilog 结构中。Verilog HDL 与VHDL相比，有更少的保留字（关键字）。而我们实际编码使用的保留字就更少了。 Verilog ＨDL 是如此的又好又对。
		1 module counter (clk,rst,enable,count); 2 input clk, rst, enable; 3 output [3:0] count; 4 reg [3:0] count; 5 6 always @ (posedge clk or posedge rst) 7 if (rst) begin 8 count <= 0; 9 end else begin : COUNT 10 while (enable) begin 11 count <= count + 1; 12 disable COUNT; 13 end 14 end 15 16 endmodule You could download file one_day5.v here
		The example above uses most of the constructs of Verilog. You'll notice a new block called always - this illustrates one of the key features of Verilog. Most software languages, as we mentioned before, execute sequentially - that is, statement by statement. Verilog programs, on the other hand, often have many statements executing in parallel. All blocks marked always will run - simultaneously - when one or more of the conditions listed within it is fulfilled. 上面这个例子中使用了Verilog HDL中的大多数的结构。你将会注意到一个新的称之为always的块，它阐述了Verilog中的一个重要特性。大多数软件编程语言，前面提到的都是顺序执行的即逐句执行的。另外一方面, 在Verilog HDL程序中，有许多语句时并行执行的。 所有的标记为always的代码块都同时运行-当其中一个或多个条件语句得到满足时。
		In the example above, the always block will run when either rst or clk reaches a positive edge - that is, when their value has risen from 0 to 1. You can have two or more always blocks in a program going at the same time (not shown here, but commonly used). 在上面这个例子中，这个always block将在rst或者clk到达正沿时运行。也就是说，当他们的值从0上升到1时。 你可以在一个程序中两个或多个always 块同时运行（这儿没有显示，但是非常通用）。
		We can disable a block of code, by using the reserve word disable. In the above example, after each counter increment, the COUNT block of code (not shown here) is disabled. 我们可以使用保留字 disable 来禁用一个代码块。 在上面的例子中，在每次counter 加1后，这个COUNT block被禁用， 去使能。

		For loop  // for 循环
		For loops in Verilog are almost exactly like for loops in C or C++. The only difference is that the ++ and -- operators are not supported in Verilog. Instead of writing i++ as you would in C, you need to write out its full operational equivalent, i = i + 1. Verilog HDL 中的for loop和C、C++中的几乎完全一样。 唯一的不同是Verilog HDL不支持++和--操作符。 作为C语言中i++的替代品， 你需要写出其全操作数的等价体： i = i + 1；
		1 for (i = 0; i < 16; i = i +1) begin 2 $display ("Current value of i is %d", i); 3 end You could download file one_day6.v here
		This code will print the numbers from 0 to 15 in order. Be careful when using for loops for register transfer logic (RTL) and make sure your code is actually sanely implementable in hardware... and that your loop is not infinite. 这个code将按序打印0 到15的值。当在RTL级使用for loop时要小心确保，你的代码是真正能够用硬件健壮地实现，并且你的for loop不是死循环。
		Repeat // repeat 语句
		Repeat is similar to the for loop we just covered. Instead of explicitly specifying a variable and incrementing it when we declare the for loop, we tell the program how many times to run through the code, and no variables are incremented (unless we want them to be, like in this example). repeat 和刚才学习for loop非常相似。不需要像for loop中显示地指派一个变量用与自增，在repeat语句中只需要告诉程序重复执行的次数。没有变量增加。
		1 repeat (16) begin 2 $display ("Current value of i is %d", i); 3 i = i + 1; 4 end You could download file one_day7.v here
		The output is exactly the same as in the previous for-loop program example. It is relatively rare to use a repeat (or for-loop) in actual hardware implementation. 这个输出和前一个for-loop例子的输出是一样的。在真正的硬件实现中 repeat 和for-loop使用的相对较少。
		Summary //总结
		While, if-else, case(switch) statements are the same as in C language.  //while、if-else、case（switch） 和C语言中的系统 If-else and case statements require all the cases to be covered for combinational logic. //组合逻辑电路设计中，if-else和case 语句中要包含所有情形。 For-loop is the same as in C, but no ++ and -- operators. // for-loop和C语言中的一致，只是没有++和--操作符。 Repeat is the same as the for-loop but without the incrementing variable. //repeat和for-loop一样，但是不许要变量的自增。
		Variable Assignment // 变量的赋值
		In digital there are two types of elements, combinational and sequential. Of course we know this. But the question is "How do we model this in Verilog ?". Well Verilog provides two ways to model the combinational logic and only one way to model sequential logic. 在数字电路中，有两类成员，组合的和时序的。当然我们了解这些。 但是问题是如何用Verilog HDL对它们建模？ 然而， Verilog HDL中提供了两种对组合逻辑电路建模的方法，但对于时序逻辑电路的建模的方法只有一种。
		Combinational elements can be modeled using assign and always statements. 组合电路可以通过 assign语句和always语句块实现建模。 Sequential elements can be modeled using only always statement. 时序电路只能通过always语句块建模； There is a third block, which is used in test benches only: it is called Initial statement. 第三种语句块，只用于test bench，测试基准，就是 initial 语句块。
		Initial Blocks // initial 语句块
		An initial block, as the name suggests, is executed only once when simulation starts. This is useful in writing test benches. If we have multiple initial blocks, then all of them are executed at the beginning of simulation. 一个initial 语句块，正如其名字暗示的，只在simulation（仿真）开始时，执行。这个initial block对写测试基准，非常有效。 如果我们有多个initial block，则他们都在simulation（仿真）开始时，执行。
		Example
		1 initial begin 2 clk = 0; 3 reset = 0; 4 req_0 = 0; 5 req_1 = 0; 6 end You could download file one_day8.v here
		In the above example, at the beginning of simulation, (i.e. when time = 0), all the variables inside the begin and end block are driven zero. 在上面的例子中，在仿真(simulation)的开始(即 当time=0时）， 所有的在begin和end之间的变量的都被驱动为0.
		Go on to the next page for the discussion of assign and always statements. 接着在下一页将讨论assignment语句和always语句。

the original link:http://www.asic-world.com/verilog/verilog_one_day2.html