赛灵思的HDMI Receiver Subsystem 用户手册pg236翻译和学习(4)

读赛灵思IP手册，HDMI 1.4/2.0 Receiver Subsystem v2.0 Product Guide，即HDMI接受器系统的手册。本期介绍HDCP高带宽数字内容保护。

HDCP

As part of the HDMI RX Subsystem, the Xilinx® LogiCORE™ IP High-bandwidth Digital Content Protection (HDCP™) receivers are designed for receiving of audiovisual content securely between two devices that are HDCP capable. In this HDMI RX Subsystem, both HDCP 1.4 and HDCP 2.2 Receiver IP cores are included. However because HDCP 2.2 supersedes the HDCP 1.4 protocol and does not provide backwards compatibility, you need to decide and choose targeted content protection schemes from the Vivado IDE. Four different options are available to choose from:

高带宽数字内容保护（HDCP）

作为HDMI RX子系统的一部分，Xilinx®LogiCORE™ IP高带宽数字内容保护（HDCP™) 接收器设计用于在两个支持HDCP的设备之间安全地接收视听内容。在此HDMI RX子系统中，包括HDCP 1.4和HDCP 2.2接收机IP核。但是，由于HDCP 2.2取代了HDCP 1.4协议，并且不提供向后兼容性，因此您需要从Vivado IDE中决定并选择目标内容保护方案。有四种不同的选项可供选择：

• No HDCP

• HDCP 1.4 only

• HDCP 2.2 only

• HDCP 1.4 and HDCP 2.2

As a guideline, HDCP 2.2 is used to decrypt content at Ultra-High Definition (UHD) while HDCP 1.4 is the legacy content protection scheme used at lower resolutions.

Figure 2-6 shows a configuration of the HDMI receiver where both HDCP 1.4 and 2.2 are enabled. With both HDCP protocols enabled, the HDMI Subsystem configures itself in the cascade topology where the HDCP 1.4 and HDCP 2.2 are connected back-to-back. The HDCP Egress interface of the HDMI receiver sends encrypted audiovisual data, which is decrypted by the active HDCP block and sent back into the HDMI receiver over the HDCP Ingress interface to send to other video processing modules in the system through AXI4-Stream Video interface or Native Video interface. The HDMI receiver subsystem ensures that only one of the HDCP protocols are active at any given time and the other is passive by calling the relevant HDMI RX Subsystem API functions.

作为指导原则，HDCP 2.2用于以超高清晰度（UHD）解密内容，而HDCP 1.4是以较低分辨率使用的传统内容保护方案。

图2-6显示了启用HDCP 1.4和2.2的HDMI接收器的配置。启用两个HDCP协议后，HDMI子系统在级联拓扑中进行自我配置，其中HDCP 1.4和HDCP 2.2背靠背连接。HDMI接收器的HDCP出口接口发送加密的视听数据，这些数据由活动HDCP块解密，并通过HDCP入口接口发送回HDMI接收器，以通过AXI4流视频接口或本机视频接口发送到系统中的其他视频处理模块。HDMI接收器子系统通过调用相关HDMI RX子系统API功能，确保在任何给定时间只有一个HDCP协议处于活动状态，而另一个则处于被动状态。

Standards

The HDMI 1.4/2.0 Receiver Subsystem is compliant with the AXI4-Stream Video Protocol and AXI4-Lite interconnect standards. See the Vivado AXI Reference Guide (UG1037) [Ref 1] for additional information. Also, see HDMI specifications [Ref 10].

The HDMI RX Subsystem is compliant with the HDMI 1.4b and HDMI 2.0 specification [Ref 10].

The Xilinx HDCP 1.4 is designed to be compatible with High-bandwidth Digital Content Protection system Revision 1.4 [Ref 11].

The Xilinx HDCP 2.2 is compliant with the HDCP 2.2 specification entitled High-bandwidth Digital Content Protection, Mapping HDCP to HDMI, Revision 2.2, issued by Digital Content Protection (DCP) LLC [Ref 11]

标准

HDMI 1.4/2.0接收器子系统符合AXI4流视频协议和AXI4 Lite互连标准。更多信息，请参见《Vivado AXI参考指南》（UG1037）[参考文献1]。另请参阅HDMI规范[参考文献10]。

HDMI RX子系统符合HDMI 1.4b和HDMI 2.0规范[参考文献10]。

Xilinx HDCP 1.4设计为与高带宽数字内容保护系统版本1.4兼容[参考文献11]。

Xilinx HDCP 2.2符合数字内容保护（DCP）LLC发布的题为“高带宽数字内容保护，将HDCP映射到HDMI，2.2版”的HDCP 2.2规范[参考文献11]

Performance

For full details about performance and resource utilization, visit the Performance and Resource Utilization web page.

性能

有关性能和资源利用率的完整详细信息，请访问性能和资源使用率网页。

Maximum Frequencies

Refer to the following documents for information on DC and AC switching characteristics. The frequency ranges specified in these documents must be adhered to for proper transceiver and core operation.

最大频率

有关直流和交流开关特性的信息，请参阅以下文档。必须遵守这些文件中规定的频率范围，以确保正确的收发器和核心操作。

• Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) [Ref 2]

• Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) [Ref 3]

• Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182) [Ref 4]

• Virtex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS183) [Ref 5]

• Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS181) [Ref 6]

• Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922) [Ref 7]

• Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS923) [Ref 8]

• Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 9]

•Kintex UltraScale FPGA数据表：直流和交流开关特性（DS892）[参考文献2]

•Virtex UltraScale FPGA数据表：直流和交流开关特性（DS893）[参考文献3]

•Kintex-7 FPGA数据表：直流和交流开关特性（DS182）[参考文献4]

•Virtex-7 FPGA数据表：直流和交流开关特性（DS183）[参考5]

•第7条FPGA数据表：直流和交流开关特性（DS181）[参考文献6]

•Kintex UltraScale+FPGA数据表：直流和交流开关特性（DS922）[参考文献7]

•Virtex UltraScale+FPGA数据表：直流和交流开关特性（DS923）[参考文献8]

•Zynq UltraScale+MPSoC数据表：直流和交流开关特性（DS925）[参考文献9]