自动饮料售卖机Verilog设计

饮料为5美分，饮料机只能接收1美分，2美分，5美分的钱币，请设计一个Verilog电路表示

`timescale 1ns/10ps
module sell(one,two,five,rset,clk,result);
input one,two,five,rset,clk;
output result;
reg drink;
assign result = drink;
reg [2:0] current_state,next_state;
parameter [2:0]
  S0 = 3'b000,
  S1 = 3'b001,
  S2 = 3'b010,
  S3 = 3'b011,
  S4 = 3'b100;
//sequential state transition
always @ (posedge clk or negedge rset)
  if (!rset)
    current_state <= S0;
  else
    current_state <= next_state;
always@(current_state or one or two or five)
begin
  case(current_state)
    S0: begin
      drink = 1'b0;
      if(one == 1)
      begin
        next_state = S1;
        drink = 0;
      end
      else if(two == 1)
      begin
        next_state = S2;
        drink = 0;
      end
      else if(five == 1)
      begin
        next_state = S0;
      drink = 1;
      end
      else
      begin
        next_state = S0;
        drink = 0;
       end
    end
    S1:
    begin
      drink = 1'b0;
      if(one == 1 )
      begin
        next_state = S2;
        drink = 0;
      end
      else if(two == 1)
      begin
        next_state = S3;
        drink = 0;
      end
      else
      begin
        next_state = S1;
        drink = 0;
      end
    end
    S2:
    begin
       drink = 1'b0;
      if(one == 1)
      begin
        next_state = S3;
        drink = 0;
      end
      else if(two == 1)
      begin
        next_state = S4;
        drink = 0;
      end
      else
      begin
        next_state = S2;
        drink = 0;
      end
    end
    S3:
    begin
        drink = 1'b0;
      if(one == 1)
      begin
        next_state = S4;
        drink = 0;
      end
      else if(two == 1)
      begin
        next_state = S0;
        drink = 1;
      end
      else
      begin
        next_state = S3;
        drink = 0;
      end
    end
    S4:
    begin
        drink = 1'b0;
      if(one == 1)
      begin
        next_state = S0;
        drink = 1;
      end
      else
      begin
        next_state = S4;
        drink = 0;
      end
    end
  endcase
  end
  endmodule

测试程序如下：

仿真波形：