Cadence17.2 ＞ OrCAD Capture CIS ＞ 设计规则检查（Design Rule Check）DRC学习记录详解

目录

一、Design Rule Check对话框选项详解

1）Design Rule Options选项详解

2）Electrical Rules（电气规则检查）选项详解

3）Physical Rules（物理规则检查）选项详解

4）ERC Matrix tab（ERC 矩阵选项卡）选项详解

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选中设计完成的DSN文件，选择Tool->Design Rule Check，弹出下面对话框，详解如下。

一、Design Rule Check对话框选项详解

Design Rules Options tab	Set the scope, mode and type of design rule (electrical and / or physical) test options for the design rules check.	为设计规则检查设置设计规则（电气和/或物理）测试选项的范围、模式和类型。
Electrical Rules tab	Set the electrical design rule checks and reports to be generated from the check.	设置电气设计规则检查和从检查生成的报告。
Physical Rules tab	Set the physical design rule checks and reports to be generated from the check.	设置物理设计规则检查和从检查生成的报告。
ERC Matrix tab	Set the matrix rules used during the design rules check.	设置在设计规则检查期间使用的矩阵规则。

 

1）Design Rule Options选项详解

Scope	Select the scope of the design rules check. The scope can cover the entire design, or the selected schematic folder. If you run Design Rules Check on a single schematic page, Capture checks all pages in the entire schematic folder, which ensures that all nets on the schematic page are valid.	选择设计规则检查的范围。范围可以覆盖整个设计或选定的原理图文件夹。 如果在单个原理图页面上运行设计规则检查，Capture 会检查整个原理图文件夹中的所有页面，以确保原理图页面上的所有网络均有效。
Mode	Specify to check either instances or occurrences. Capture automatically sets this option based on the project type. All designs default to use instances. If a PCB or Schematic design is complex or has occurrence properties, the default shifts to occurrences. Capture recommends the preferred mode, which you can override.	指定检查实例或事件。 Capture 会根据项目类型自动设置此选项。所有设计默认使用实例。如果 PCB 或原理图设计很复杂或具有出现属性，则默认设置为出现。 Capture 推荐首选模式，您可以覆盖该模式。
Action	Specifies either a design rules check, deletion of existing DRC markers or creating DRC markers for warning. The DRC markers are automatically deleted when you run a subsequent design rules check. Use the Ignore DRC Warnings option to specify any DRC Warnings that you do not want to be checked during the DRC check and netlisting. For example, to ignore the ALG0051 or ALG0016 warnings during netlist, specify these in the Ignore Warnings dialog. You can select the Preserve waived DRC to retain the DRC waiver settings for a design. When you waive a DRC, it is not included in the DRC report. Setting this option ensures that the waived DRCs are not shown when you run DRC on the design.	指定设计规则检查、删除现有 DRC 标记或创建警告的 DRC 标记。 当您运行后续设计规则检查时，会自动删除 DRC 标记。 使用 Ignore DRC Warnings 选项指定在 DRC 检查和网表列出期间不希望检查的任何 DRC 警告。例如，要在网表期间忽略 ALG0051 或 ALG0016 警告，请在“忽略警告”对话框中指定这些警告。 您可以选择 Preserve waived DRC 以保留设计的 DRC 豁免设置。当您放弃 DRC 时，它不会包含在 DRC 报告中。设置此选项可确保在设计上运行 DRC 时不会显示放弃的 DRC。
Design Rules	Select the type of rules to run, electrical and / or physical.	选择要运行的规则类型，电气和/或物理。
Report file	Specify the path and file name for the report.	指定报告的路径和文件名。
View Output	Open the design rules check report file in a text editor.	在文本编辑器中打开设计规则检查报告文件。
Browse	Displays a standard Windows dialog box for selecting files.	显示用于选择文件的标准 Windows 对话框。

 

2）Electrical Rules（电气规则检查）选项详解

Electrical Rules（电气规则检查）
Check single node nets	Check if the design contains any nets with only one connection.	检查设计是否包含任何只有一个连接的网络。
Check no driving source and Pin type conflicts		检查无驱动源和引脚类型冲突
Check duplicate net names	Check if the design contains any duplicate net names.	检查设计是否包含任何重复的网络名称。
Check off-page connector connections	Verify that off-page connector nets on a schematic page match those on other schematic pages.	验证原理图页面上的页外连接器网络是否与其他原理图页面上的匹配。
Check hierarchical port connections	Verify that hierarchical pins in a hierarchical block match hierarchical ports in the child schematic folder or folders. Errors are generated if the number of hierarchical ports and hierarchical pins differ between the parent and child schematic folders. Also generates errors if the types of hierarchical ports are not identical between the parent and child schematic folders.	验证分层模块中的分层引脚是否与子原理图文件夹中的分层端口匹配。如果父原理图文件夹和子原理图文件夹之间的分层端口和分层引脚的数量不同，则会生成错误。如果父逻辑示意图文件夹和子逻辑示意图文件夹之间的分层端口类型不同，也会产生错误。
Check unconnected bus nets	Check for and reports all unconnected bus nets. This check will run for all unconnected bus nets across schematics in a design.	检查并报告所有未连接的总线网络。此检查将针对设计中原理图上的所有未连接的总线网络运行。
Check unconnected pins	Check for any pins on the design that are unconnected or do not have no-connect attached.	检查设计上是否有任何未连接或未连接的引脚。
Check SDT compatibility	Check for SDT compatibility.	检查 SDT 兼容性。

 

Custom DRC
Run custom DRC	Select to run custom DRCs.	选择运行自定义 DRC。
Configure Custom DRC	Click to launch the Custom Design Rule Checker to select custom TCL DRCs that you want to run.	单击以启动自定义设计规则检查器以选择要运行的自定义 TCL DRC。

Reports
Report all net names	List the names of all nets in the report file.	列出报告文件中所有网络的名称。
Report off-grid objects	List all objects that are on Fine grid in the report file.	列出报告文件中精细网格上的所有对象。
Report hierarchical ports and off-page connectors	List all hierarchical ports and off-page connectors in the report file.	列出报告文件中的所有分层端口和页外连接器。
Report misleading tap connections	Checks for and reports those signals that are wrongly connected through a Bus Tap to a bus. Also checks for missing bus taps.	检查并报告那些通过总线分路器错误连接到总线的信号。还检查缺少的总线分接头。

 

3）Physical Rules（物理规则检查）选项详解

 

Physical Rules
Check power pin visibility	Check if the visibility property of a power pin on one section of multi-section part is different from the corresponding power pin on another section of the part.	检查多段零件的一个部分上的电源引脚的可见性属性与零件另一部分上相应的电源引脚的可见性属性是否不同。
Check missing/illegal PCB Footprint property	Check if the PCB footprint property on a part is missing or the property defined is illegal.	检查部件上的 PCB 封装属性是否缺失或定义的属性是否非法。
Check Normal Convert view sync	Check if the pin numbers on the normal view of a part are different from the pin numbers on the convert view.	检查零件正常视图上的引脚编号是否与转换视图上的引脚编号不同。
Check incorrect Pin_Group assignment	Check if all pins in same pin group in a part are of the same type.	检查零件中同一引脚组中的所有引脚是否为同一类型。
Check high speed props syntax	Check the syntax of the high speed properties of the nets in the design.	检查设计中网络的高速属性的语法。
Check missing pin numbers	Check if any part on the design has missing pin numbers.	检查设计中是否有任何部分缺少引脚号。
Check device with zero pins	Check if any part on the design has no pin on the part.	检查设计上的任何部件是否在部件上没有引脚。
Check power ground short	Check if the type of power pin name inside a part is connected to a net on the schematic with a different name.	检查部件内的电源引脚名称类型是否连接到原理图上具有不同名称的网络。
Check Name Prop consistency	Check if the occurrences of a hierarchical block have the same "Name" property.	检查分层块的出现是否具有相同的“名称”属性。

Reports
Report Visible unconnected power pins	List the names of all visible unconnected power pins.	列出所有可见的未连接电源引脚的名称。
Report unused part packages	List the names of any unused part packages.	列出任何未使用的零件包的名称。
Report invalid packaging	List any invalid packaging.	列出任何无效的包装。
Report identical part references	List any identical part references.	列出所有相同的零件参考。

 

4）ERC Matrix tab（ERC 矩阵选项卡）选项详解

Matrix	Set the rules used by the Design Rules Check when testing connections between pins, hierarchical blocks, and hierarchical ports. The pins, hierarchical ports, and off-page connectors are listed in columns and rows in the table. A test is represented by the intersection of a row and column. Either the intersection of a row and column is empty, or it contains a "W" or an "E." An empty intersection represents a valid connection, a "W" is a warning, and an "E" represents an error. You can cycle through these three settings by pointing to an intersection and clicking the mouse button until the desired setting displays. You can also type W for warning, E for error, and N for an empty intersection. In addition to these keys, you can use the arrow keys to select other intersections.	设置设计规则检查在测试引脚、分层模块和分层端口之间的连接时使用的规则。 引脚、分层端口和页外连接器列在表的列和行中。测试由行和列的交集表示。行和列的交叉点要么是空的，要么包含“W”或“E”。空交点代表有效连接，“W”代表警告，“E”代表错误。 您可以通过指向一个交叉点并单击鼠标按钮来循环浏览这三个设置，直到显示所需的设置。您还可以输入 W 表示警告，E 表示错误，N 表示空交叉点。除了这些键之外，您还可以使用箭头键来选择其他交叉点。
Restore defaults	Restore the ERC matrix to its default values.	将 ERC 矩阵恢复为其默认值。

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