[HDLBits] Module shift

You are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances.

The module provided to you is: module my_dff ( input clk, input d, output q );

Note that to make the internal connections, you will need to declare some wires. Be careful about naming your wires and module instances: the names must be unique.

module top_module ( input clk, input d, output q );
    wire q1,q2;
    my_dff d1(clk,d,q1);
    my_dff d2(clk,q1,q2);
    my_dff d3(clk,q2,q);
endmodule

 这里就很有意思，不需要用assign赋值就可以给wire类型赋值，这是直接通过my_dff的输出赋值实现的。