Fsm1s

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1, but using synchronous reset.

 

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
	parameter A = 2'b00;
    parameter B = 2'b01;
    
    reg present_state, next_state;

    assign out = next_state == B ? 1'b1 : 1'b0;
     	
    always @(*)
        next_state <= present_state;
        
    always @(posedge clk) begin
        if (reset) begin  
            // Fill in reset logic
            present_state <= B; 
        end else begin
            case (present_state)
                // Fill in state transition logic
                B: if(in == 0)
                    	present_state <= A;
                	else 
                        present_state <= B;
                A: if(in == 0)
                    	present_state <= B;
                	else 
                        present_state <= A;
                
                   default: present_state <= B;
            endcase 
        end
    end

endmodule