DDR3介绍
DDR3芯片以 镁光(Micron) 的 MT41J256M16为例:
MT41J256M16 – 32 Meg x 16 x 8 banks:在我看来,一共能存储256M的16位数,一共4G。
命名规则
要注意的在Configuration和Speed Grade两项。规定了存储配置和时钟速度。
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes.
DQS信号在写时,是与data中心对齐的;在读时,是边缘对齐的(也就是一起开始传输)。
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access.
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
写和读都是突发传输的,突发长度可以是BL8和BC4,在发送读命令和写命令时,可以通过A12/BC#引脚进行切换。
芯片资料中还有一堆参数,电路的,用于时序分析的,还有命令和读写时序等。如果使用xilinx IP核mig进行开发,如果有这种芯片型号,这些都会自动配置好;没有的话,就得自己根据参数进行配置。
芯片资料暂时就了解到这里。。。
开发板原理图:
采用两片DDR3将数据位宽变成32位,地址和控制管脚共用,DQ、DQS、DM信号分开。
MIG IP配置:
(Clock Period)这里注意运行频率是所给时钟的两倍,即CLK是400M的,但是跑起来是800M。
此速度也是会受到FPGA和器件速度等级等因素的限制。
PHY to Controller Clock Ratio自动生成,这里显示为4:1,那么,用户时钟就是100M的(IP例化时的ui_clk信号)。
2.Memory Address Mapping Selection:BANK、ROW、COLUMN.
3.这里还要注意突发长度:
只支持BL8突发传输,所以32bits的数据接口,在用户端,每次就是32*8=256bits(app_wdf_data变量是256位的)。
System Reset Polarity:选择的是低有效,例化时要注意。
配置详情要参考手册UG586。
Block Diagram:
利用MIG IP核,我们只需要关注用户侧,User Interface。与DDR芯片连接的物理管脚,我们只需要知道约束就行。
在我的设计中,地址信号如下所示。
wire [28:0] app_addr; //([0:0]Rank, [2:0]bank, [14:0]row, [9:0]colum)
在DDR中写数,然后读出,效果不错。随着状态机的优化,读出的时序好了很多,基本上连续。