PLL原语例化使用时常见问题

目录

一、前言

二、常见问题

问题一、综合阶段报错[Synth 8-439]

问题二、综合阶段报错[Synth 8-448] 

问题三、在实现阶段DRC报错DRC PDRC-38

问题四、在实现阶段DRC报错DRC PDRC-43


一、前言

    在设计中经常会使用PLL的原语进行例化使用,PLL如果直接例化使用将会报错,以PLLE2_ADV为例,vivado版本为2019.1,器件为xc7k480tffv1156,例化的模版如下,下面4个标红的系数需重点关注。

  PLLE2_ADV #(

      .BANDWIDTH("OPTIMIZED"),  // OPTIMIZED, HIGH, LOW

      .CLKFBOUT_MULT(5),        // Multiply value for all CLKOUT, (2-64)将输出先进行指定倍数的倍频处理

      .CLKFBOUT_PHASE(0.0),     // Phase offset in degrees of CLKFB, (-360.000-360.000).

      // CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).

      .CLKIN1_PERIOD(0.0),

      .CLKIN2_PERIOD(0.0),

      // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)  设置输出时钟的分频系数

      .CLKOUT0_DIVIDE(1),

      .CLKOUT1_DIVIDE(1),

      .CLKOUT2_DIVIDE(1),

      .CLKOUT3_DIVIDE(1),

      .CLKOUT4_DIVIDE(1),

      .CLKOUT5_DIVIDE(1),

      // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).设置输出时钟的占空比

      .CLKOUT0_DUTY_CYCLE(0.5),

      .CLKOUT1_DUTY_CYCLE(0.5),

      .CLKOUT2_DUTY_CYCLE(0.5),

      .CLKOUT3_DUTY_CYCLE(0.5),

      .CLKOUT4_DUTY_CYCLE(0.5),

      .CLKOUT5_DUTY_CYCLE(0.5),

      // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).设置输出时钟的相移值

      .CLKOUT0_PHASE(0.0),

      .CLKOUT1_PHASE(0.0),

      .CLKOUT2_PHASE(0.0),

      .CLKOUT3_PHASE(0.0),

      .CLKOUT4_PHASE(0.0),

      .CLKOUT5_PHASE(0.0),

      .COMPENSATION("ZHOLD"),   // ZHOLD, BUF_IN, EXTERNAL, INTERNAL

      .DIVCLK_DIVIDE(1),        // Master division value (1-56)

      // REF_JITTER: Reference input jitter in UI (0.000-0.999).

      .REF_JITTER1(0.0),

      .REF_JITTER2(0.0),

      .STARTUP_WAIT("FALSE")    // Delay DONE until PLL Locks, ("TRUE"/"FALSE")

   )

   PLLE2_ADV_inst (

      // Clock Outputs: 1-bit (each) output: User configurable clock outputs

      .CLKOUT0(CLKOUT0),   // 1-bit output: CLKOUT0

      .CLKOUT1(CLKOUT1),   // 1-bit output: CLKOUT1

      .CLKOUT2(CLKOUT2),   // 1-bit output: CLKOUT2

      .CLKOUT3(CLKOUT3),   // 1-bit output: CLKOUT3

      .CLKOUT4(CLKOUT4),   // 1-bit output: CLKOUT4

      .CLKOUT5(CLKOUT5),   // 1-bit output: CLKOUT5

      // DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports

      .DO(DO),             // 16-bit output: DRP data

      .DRDY(DRDY),         // 1-bit output: DRP ready

      // Feedback Clocks: 1-bit (each) output: Clock feedback ports

      .CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock

      .LOCKED(LOCKED),     // 1-bit output: LOCK

      // Clock Inputs: 1-bit (each) input: Clock inputs

      .CLKIN1(CLKIN1),     // 1-bit input: Primary clock

      .CLKIN2(CLKIN2),     // 1-bit input: Secondary clock

      // Control Ports: 1-bit (each) input: PLL control ports

      .CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2

      .PWRDWN(PWRDWN),     // 1-bit input: Power-down

      .RST(RST),           // 1-bit input: Reset

      // DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports

      .DADDR(DADDR),       // 7-bit input: DRP address

      .DCLK(DCLK),         // 1-bit input: DRP clock

      .DEN(DEN),           // 1-bit input: DRP enable

      .DI(DI),             // 16-bit input: DRP data

      .DWE(DWE),           // 1-bit input: DRP write enable

      // Feedback Clocks: 1-bit (each) input: Clock feedback ports

      .CLKFBIN(CLKFBIN)    // 1-bit input: Feedback clock

   );

二、常见问题

工程设计代码,主要关注前面 PLLE2_ADV例化使用的参数配置。

module sdc_constraint
(
    input rst_pll,
    input d0,
    input d1,
    output out0,
    output out1,

    input CLK,
    input RSTn,   
    output SDRAM_CLK,
    output [4:0]SDRAM_CMD,
    output [13:0]SDRAM_BA,
    inout [15:0]SDRAM_DATA,

    input CLK1,	
	input WrEN_Sig,
	input RdEN_Sig,
	output Done_Sig,
	output Busy_Sig,	
	input Init_Done_Sig,
	output Init_Start_Sig,
	output [2:0]Func_Start_Sig,   
    output SDRAM_UDQM,
    output SDRAM_LDQM,

    input CLK2,
    input [3:0]Din,
    output [3:0]Dout


);

     /***********PLL*****************/
	 
	 wire CLK0_PLL;
	 wire CLK1_PLL;
	 reg ff0_pll,ff1_pll;
	 reg out0,out1;
	 
	 PLLE2_ADV
	 #(
	  .CLKFBOUT_MULT(5),        // Multiply value for all CLKOUT, (2-64)
      .CLKOUT0_DIVIDE(2),         // Divide amount for CLKOUT0 (1-128)
      .CLKOUT0_DUTY_CYCLE(0.3),   // Duty cycle for CLKOUT0 (0.001-0.999)
      .CLKOUT0_PHASE(0.0), 
      .CLKOUT1_DIVIDE(3),         // Divide amount for CLKOUT0 (1-128)
      .CLKOUT1_DUTY_CYCLE(0.7),   // Duty cycle for CLKOUT0 (0.001-0.999)
      .CLKOUT1_PHASE(0.0)   
	 	)
	 U1

	 (
	     	.CLKIN1 ( CLK ),
	        .CLKOUT0 ( CLK0_PLL ),
	        .CLKOUT1 ( CLK1_PLL )
	 );
	 /**********FF0**********/ 
	 always@(posedge CLK0_PLL,negedge rst_pll)
	 	if(!rst_pll)
	 		ff0_pll<=0;
	 	else begin
	 		ff0_pll<=d0;
	 	end

	 assign result0=ff0_pll&Busy_Sig;

	 always@(posedge CLK0_PLL,negedge rst_pll)
	 	if(!rst_pll)
	 		out0<=0;
	 	else begin
	 		out0<=result0;
	 	end

	 /**********FF1**********/ 
	 always@(posedge CLK1_PLL,negedge rst_pll)
	 	if(!rst_pll)
	 		ff1_pll<=0;
	 	else begin
	 		ff1_pll<=d0;
	 	end

	 assign result1=ff1_pll^Done_Sig;

	 always@(posedge CLK1_PLL,negedge rst_pll)
	 	if(!rst_pll)
	 		out1<=0;
	 	else begin
	 		out1<=result1;
	 	end


	 /********************************/
   /*******************SDRAM**************/
    	
	parameter T15US = 11'd1500;
	
	/*********************************/
	
	reg [2:0]i;
	reg [10:0]C1;
	reg [4:0]C2;
	reg [4:0]Used;
    reg [2:0]rStart;
	reg [2:0]isStart; //[2] Auto Refresh , [1] Read Action, [0] Write Action
	reg isInit;
	reg isBusy;
	reg isDone;
	
	always @ ( posedge CLK1 or negedge RSTn )
	    if( !RSTn )
		     begin
		            i <= 3'd6;          // Initial SDRam at first 
		            C1 <= 11'd0;
		            C2 <= 5'd0;
		            Used <= 5'd0;
		            rStart <= 3'b000;
					isStart <= 3'b000;
					isInit <= 1'b0;
					isBusy <= 1'b1;
					isDone <= 1'b0;
			  end
		 else 
		     case( i )
			  
					0: // IDLE state
					if( C1 >= T15US ) begin C1 <= 11'd0; Used <= 5'd9; rStart <= 3'b100; i <= 3'd1; end
				    else if( RdEN_Sig ) begin C1 <= C1 + 1'b1; Used <= 5'd8; rStart <= 3'b010;i <= 3'd3; end 
					else if( WrEN_Sig ) begin C1 <= C1 + 1'b1; Used <= 5'd9; rStart <= 3'b001;i <= 3'd3; end 
                    else begin C1 <= C1 + 1'b1; end

                    /***************************/

					1: // Auto Refresh Done , 9 clock on this step
					if( C2 == Used -1 ) begin C2 <= 5'd0; i <= i + 1'b1; end
				    else begin isStart <= rStart; C2 <= C2 + 1'b1; end
				    
				    2: // 1 clock one this step			
				    begin isStart <= 3'd0; C1 <= C1 + 1'b1; i <= 3'd0; end
				    
				    /***************************/
				    
				    3: // Read and Write Done
					if( C2 == Used -1) begin C2 <= 5'd0; C1 <= C1 + Used; i <= i + 1'b1; end
					else begin isStart <= rStart; C2 <= C2 + 1'b1; end
					
					/***************************************/
					
					4: // Generate Done Signal
					begin isStart <= 3'd0; isDone <= 1'b1; C1 <= C1 + 1'b1; i <= i + 1'b1; end
					
					5: 
					begin isDone <= 1'b0; C1 <= C1 + 1'b1; i <= 3'd0; end
					
					/******************************************/
					
					6: // Initial SDRam using 21 clock
					if( Init_Done_Sig ) begin isBusy <= 1'b0; isInit <= 1'b0; C1 <= C1 + 1'b1; i <= 3'd0; end
				    else begin isBusy <= 1'b1; isInit <= 1'b1; end
					
					/******************************************/
					
			  endcase
			  
	/***************************************/
	
	assign Init_Start_Sig = isInit;
	assign Func_Start_Sig = isStart;
	assign Done_Sig = isDone;
	assign Busy_Sig = isBusy;
	
	/***************************************/

	 /********************************/		 
	 
    reg [3:0]rData;
    
    always @ ( posedge CLK2 or negedge RSTn )
        if( !RSTn )
            begin
                rData <= 4'd0;
            end
        else 
            begin
                rData <= Din;
            end
    
    /********************************************/
            
    assign Dout = rData;
    
    /********************************************/    
     
endmodule

问题一、综合阶段报错[Synth 8-439]

现象:具体报错内容如下

[Synth 8-439] module 'PLLE2_BASE1' not found ["C:/Users/Administrator/Desktop/verilog_test/project_4/experiment15/sdram_demo3/sdram_demo3.v":52]

PLL原语例化使用时常见问题_第1张图片

 

原因:报错信息中提示很明显,即使用了不存在的原语PLLE2_BASE1

解决:使用器件支持的原语进行例化

问题二、综合阶段报错[Synth 8-448] 

现象:具体报错内容如下

[Synth 8-448] named port connection 'CLKIN1' does not exist for instance 'U1' of module 'PLLE3_ADV' ["C:/Users/Administrator/Desktop/verilog_test/project_4/experiment15/sdram_demo3/sdram_demo3.v":55]

PLL原语例化使用时常见问题_第2张图片

 

 

原因:第一条报错已经很明了,即使用的PLLE3_ADV中CLKIN1端口在该原语中不存在,即例化使用的原语为其他器件支持的,当前器件不支持

第二条报错[Synth 8-6156] failed synthesizing module 'sdc_constraint' ["C:/Users/Administrator/Desktop/verilog_test/project_4/experiment15/sdram_demo3/sdram_demo3.v":1]是因为在约束文件sdc_constraint中对CLKIN1对应的端口进行了约束

约束内容如下

create_clock -period 10.000 -name clkin_pll -waveform {1.000 5.000} [get_ports CLK]

解决:首先在language templates中对应系列器件下是否支持PLLE3_ADV,如果不支持,将PLLE3_ADV修改为器件支持的原语,二是确认PLLE3_ADV的端口是否存在CLKIN1端口。经过确认,此处为PLLE3_ADV在当前xc7k480tffv中不支持,支持的为PLLE2_ADV,将PLLE3_ADV修改为PLLE2_ADV,使用对应的端口即可

问题三、在实现阶段DRC报错DRC PDRC-38

现象:具体报错内容如下:

[DRC PDRC-38] PLL_adv_ClkFrequency_clkin1: The calculated frequency value, 0.000 MHz, of the CLKIN1_PERIOD attribute on the PLLE2_ADV site PLLE2_ADV_X0Y0 (cell U1) is outside the allowed range (19.000 - 800.000 MHz). Please change the CLKIN1_PERIOD attribute value in order to be within the allowed range for this device.

PLL原语例化使用时常见问题_第3张图片

 

原因:未对输入端口clkin1设置时钟约束,因此默认为0MHZ

解决:对设计的输入端口CLK设置时钟约束

问题四、在实现阶段DRC报错DRC PDRC-43

具体报错内容如下

[DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 500.000 MHz (CLKIN1_PERIOD, net CLK_IBUF) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X0Y0 (cell U1) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1600.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (10.000000), multiplication factor CLKFBOUT_MULT_F (5) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

PLL原语例化使用时常见问题_第4张图片

 

原因:约束中设置的PLL的输入时钟频率与倍频系数的乘积【Hclk*CLKFBOUT_MULT】不在【800MHZ-1600MHZ】间,约束文件中CLK周期为10ns,则频率为100MHZ,PLL例化的原语中系数CLKFBOUT_MULT(5)默认为5,因此计算出的值为500MHZ,不在要求的范围内,因此报错。

约束内容:create_clock -period 10.000 -name clkin_pll -waveform {1.000 5.000} [get_ports CLK]

解决:

方法1:修改约束中CLK的周期,使其与系数CLKFBOUT_MULT的值5相乘后在【800-1600MHZ】间

方法2:修改系数CLKFBOUT_MULT的值,可将其设置为【5-16】之间的值,此处改为10,也即CLKOUT为1000MHZ

你可能感兴趣的:(FPGA所知所见所解,PLL,原语primitive,例化,常见问题)