Level Shift的影响及使用及位置

H2L ：一般放在Low Voltage，因为H2L LevelShift的supply Voltage是VDDL，如果放在High Voltage就需要将VDDL的power rail route到VDDH domain

如果高低电压差别不大，对VDDL的cell的时序影响可接受，是不需要H2L LevelShift的

L2H：同时考虑时序和电压的影响，

Level Shift放在哪个domain要看power rail和library的限制

Level Shifters

Cells used to match voltages across voltage islands

LAST UPDATED ON JANUARY 6TH, 2017

DESCRIPTION

 

Multi-supply voltage techniques require level shifters on signals that go from one voltage level to another. Without level shifters, signals that cross voltage levels will not be sampled correctly.
It is suggested that formal techniques be used in the design flow to identify missing level shifters. Finding these missing definitions early will save time in simulation and synthesis debugging.

Level shifters are added to ensure that blocks operating at different voltages will operate correctly when integrated together in the SoC. Level shifters must ensure the proper drive strength and accurate timing as signals transition from one voltage level to another. Level shifters can be inserted during the synthesis or implementation stage.

Every signal that crosses an MSV power domain should have a level shifter attached to it. Although level shifting from a higher-voltage power domain to a lower one is usually optional, level shifting from a lower-voltage power domain to a higher one is mandatory.

Level shifters are placed close to the power domain boundaries. However, level shifters have two power rails:
• Primary power rail: usually set at the top and bottom edge of the level shifter
• Secondary power rail: usually set at the center horizontal line of the level shifter

The power domain where the level shifter resides depends on which voltage the primary power rail matches. For example, if the primary power rail of the level shifter is a 0.8V rail, that level shifter should be placed in the 0.8V power domain. Therefore, some knowledge about the library is needed to decide in which power domain to place the level shifter.

Using low-power level-shifting cells can have a significant impact on timing and physical design.

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