HDLBits Count clock 答案

创建一组适合作为12小时的时钟使用的计数器(带有am/pm指示器)。你的计数器是由一个快速运行的clk驱动，时钟运行时ena必须为1，为0则暂停。reset将时钟重置到中午12点。上午时pm=0，下午时pm=1。hh，mm和ss分别是小时(01-12)、分钟(00-59)和秒(00-59)的两个BCD(二进制编码的十进制)数字。

 

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    reg [3:0] h1,h2,m1,m2,s1,s2;
    assign hh = {h2,h1};
    assign mm = {m2,m1};
    assign ss = {s2,s1};
    always@(posedge clk)begin
        if (reset)begin
        	h2<=4'h1;h1<=4'h2;
            m2<=4'h0;m1<=4'h0; 
            s2<=4'h0;s1<=4'h0;
            pm<=1'b0;
        end
        else begin
            if(ena)begin
            	if(ss==8'h59)begin
                	if(mm==8'h59)begin
                        if(hh==8'h12)begin
                           h1<=4'd1;s1<=4'd0;m1<=4'd0;
                           h2<=4'd0;s2<=4'd0;m2<=4'd0;
                        end
            			else begin
                            if(h1==4'd9)begin
                                h2<=h2+1'b1;
                           		h1<=4'd0;s1<=4'd0;m1<=4'd0; 
                           		s2<=4'd0;m2<=4'd0;
                            end
                            else begin
                                pm<=(hh==8'h11)?(pm+1'b1):pm;
                                h1<=h1+1'b1;s1<=4'd0;m1<=4'd0; 
                           		s2<=4'd0;m2<=4'd0;
                            end
                        end
                    end
                	else begin
                    	if(m1==4'd9)begin
                			m2<=m2+1'b1;m1<=4'd0;
                        	s2<=4'd0;s1<=4'd0;
                		end
               	 		else begin
                    		m1<=m1+1'b1;s1<=4'd0;s2<=4'd0;
                    	end
                	end
            	end
            	else begin
                	if(s1==4'd9)begin
                		s2<=s2+1'b1;s1<=4'd0;
                	end
                	else
                    	s1<=s1+1'b1;
            	end
            end
        end
    end
    			
endmodule

由秒针到时针依次递进。

assign语句中对输入输出进行操作后，再在块语句中直接赋值输入或输出将无法综合。