【Verilog/HDBits】

输出输入向量中1的个数

module top_module( 
    input [2:0] in,
    output [1:0] out );
    assign out = &in ? 3 : (^in ? 1 : (in ? 2 : 0));
//&in == 1 means in == 3'b111;
//^in == 1 means there are odd number of '1' 
//in == 0 means there is no "1"
endmodule

in?2:0 in不为0都取2