HDLBits答案合集（二）

本文为本人HDL刷题代码，如有问题请及时联系，本文为第三章节 Circuits答案。

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前言

本文为HDL刷题代码（二），相关文章会在博客陆续发出

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提示：以下是本篇文章正文内容，下面案例可供参考

3.1 combinational logic

3.1.1 basic gates

17个练习

3.1.1.1 Exams/m2014 q4h

module top_module (
    input in,
    output out);
    
    assign out = in;
endmodule

3.1.1.2 Exams/m2014 q4i

module top_module (
    output out);
	
    assign out = 1'b0;
endmodule

3.1.1.3 Exams/m2014 q4e

module top_module (
    input in1,
    input in2,
    output out);
    
    assign out = ~(in1 | in2);
endmodule

3.1.1.4 Exams/m2014 q4f

module top_module (
    input in1,
    input in2,
    output out);

    assign out = in1 & (~in2);
endmodule

3.1.1.5 Exams/m2014 q4g

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
    
    assign out = (~(in1 ^ in2)) ^ in3;
endmodule

3.1.1.6 gates

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    assign out_and   = a&b;
    assign out_or    = a|b;
    assign out_xor   = a^b;
    assign out_nand  = ~(a&b);
    assign out_nor	 = ~(a|b);
    assign out_xnor	 = ~(a^b);
    assign out_anotb = a&(~b);
endmodule

3.1.1.7 7420

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    assign p1y = ~(p1a & p1b & p1c & p1d);
    assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule

3.1.1.8 Truthtable1

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    always @(*)begin
        case({x3,x2,x1})
            3'b000: f=0;
            3'b001: f=0;
            3'b010: f=1;
            3'b011: f=1;
            3'b100: f=0;
            3'b101: f=1;
            3'b110: f=0;
            3'b111: f=1;
        endcase
    end
endmodule

3.1.1.9 Mt2015 eq2

module top_module ( input [1:0] A, input [1:0] B, output z ); 
    always @(*)begin
        if(A == B) z=1;
        else       z=0;
    end
endmodule

3.1.1.10 Mt2015 q4a

module top_module (input x, input y, output z);
    assign z = (x ^ y) & x;
endmodule

3.1.1.11 Mt2015 q4b

module top_module ( input x, input y, output z );
	assign z = x^~y; //同或
endmodule

3.1.1.12 Mt2015 q4

module top_module (input x, input y, output z);
	wire a1,a2,b1,b2;
    A u1(.x(x),.y(y),.z(a1));
    A u2(.x(x),.y(y),.z(a2));
    B u3(.x(x),.y(y),.z(b1));
    B u4(.x(x),.y(y),.z(b2));
    
    assign z = (a1|b1) ^ (a2&b2);
endmodule

module A (input x, input y, output z);
    assign z = (x ^ y) & x;
endmodule

module B ( input x, input y, output z );
	assign z = x^~y; //同或
endmodule

3.1.1.13 ringer

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
    assign motor = ring & vibrate_mode;
    assign ringer= ring & (~vibrate_mode);
endmodule

3.1.1.14 Thermostat

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
    assign heater = mode & too_cold;
    assign aircon = (~mode) & too_hot; 
    assign fan = heater | aircon | fan_on;
endmodule

3.1.1.15 popcount3

module top_module( 
    input [2:0] in,
    output[1:0] out );
    
    // 当作计数器来计算
    assign out = in[0] + in[1] + in[2]; 
endmodule

3.1.1.16 gatesv

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );

    // 可以直接用位运算
    assign out_both = in[3:1] & in[2:0];
    assign out_any = in[3:1] | in[2:0];
    assign out_different = in ^ {in[0],in[3:1]};
endmodule

3.1.1.17 gatesv100

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );

    assign out_both = in[98:0] & in[99:1];
    assign out_any  = in[99:1] | in[98:0];
    assign out_different = in ^ {in[0],in[99:1]};
endmodule

---

3.1.2 multiplexers

共5个练习

3.1.2.1 mux2to1

module top_module( 
    input a, b, sel,
    output reg out ); 
	
    always @(*)begin
        if(sel) out = b;
        else	out = a;
    end
endmodule

3.1.2.2 mux2to1v

module top_module( 
    input [99:0] a, b,
    input sel,
    output reg [99:0] out );
    
    always @(*)begin
        if(sel) out = b;
        else	out = a;
    end
endmodule

3.1.2.3 mux9to1v

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output reg [15:0] out );

    always @(*)begin
        case(sel)
            4'b0000: out = a;
            4'b0001: out = b;
            4'b0010: out = c;
            4'b0011: out = d;
            4'b0100: out = e;
            4'b0101: out = f;
            4'b0110: out = g;
            4'b0111: out = h;
            4'b1000: out = i;
            default: out = '1;    // '1代表每一位都置1
        endcase
    end
endmodule

3.1.2.4 mux256to1

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
	
    assign out = in[sel];
endmodule

3.1.2.5 mux256to1v

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
   
    assign out[0] = in[sel*4];
    assign out[1] = in[sel*4+1];
    assign out[2] = in[sel*4+2];
    assign out[3] = in[sel*4+3];
endmodule

---

3.1.3 arithmetic circuits

共7个练习

3.1.3.1 hadd

module top_module( 
    input a, b,
    output cout, sum );
    
    assign {cout,sum} = a+b;

endmodule

3.1.3.2 fadd

module top_module( 
    input a, b, cin,
    output cout, sum );
    
    assign {cout,sum} = a+b+cin;

endmodule

3.1.3.3 adder3

module top_module( 
    input [2:0] a, b,
    input cin,
    output [2:0] cout,
    output [2:0] sum );

    adder q1(.a(a[0]),.b(b[0]),.cin(cin),.sum(sum[0]),.cout(cout[0]));
    adder q2(.a(a[1]),.b(b[1]),.cin(cout[0]),.sum(sum[1]),.cout(cout[1]));
    adder q3(.a(a[2]),.b(b[2]),.cin(cout[1]),.sum(sum[2]),.cout(cout[2]));
endmodule
    
module adder(
	input a,b,cin,
    output cout,sum);
    assign {cout,sum} = a+b+cin;
endmodule

3.1.3.4 Exams/m2014 q4j

module top_module (
	input [3:0] x,
	input [3:0] y,
	output [4:0] sum
);
	assign sum = x+y;	// Verilog addition 
endmodule

3.1.3.5 Exams/ece241 2014 q1c

module top_module (
    input [7:0] a,
    input [7:0] b,
    output [7:0] s,
    output overflow
); //
    assign s = a+b;
    assign overflow = (a[7] & b[7] & ~s[7]) | (~a[7] & ~b[7] & s[7]);           // 符号溢出为只有两种情况

endmodule

3.1.3.6 adder100

module top_module( 
    input [99:0] a, b,
    input cin,
    output cout,
    output [99:0] sum );
    
    assign {cout,sum} = a+b+cin;

endmodule

3.1.3.7 bcdadd4

// 用两种方式解答
// 1.逐步例化
module top_module( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    
    wire [2:0] c;
    bcd_fadd q1(.a(a[3:0]),.b(b[3:0]),.cin(cin),.cout(c[0]),.sum(sum[3:0]));
    bcd_fadd q2(.a(a[7:4]),.b(b[7:4]),.cin(c[0]),.cout(c[1]),.sum(sum[7:4]));
    bcd_fadd q3(.a(a[11:8]),.b(b[11:8]),.cin(c[1]),.cout(c[2]),.sum(sum[11:8]));
    bcd_fadd q4(.a(a[15:12]),.b(b[15:12]),.cin(c[2]),.cout(cout),.sum(sum[15:12]));
endmodule

//2.用generate循环例化
module top_module( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    
    wire [3:0] c;
    bcd_fadd q1(.a(a[3:0]),.b(b[3:0]),.cin(cin),.cout(c[0]),.sum(sum[3:0]));
	
    genvar i;
    generate
        for(i=1;i<4;i=i+1)begin:bcd
            bcd_fadd q2(.a(a[4*i+3:4*i]),.b(b[4*i+3:4*i]),.cin(c[i-1]),.cout(c[i]),.sum(sum[4*i+3:4*i]));
        end
    endgenerate
    assign cout = c[3];

endmodule

3.1.4 karnaugh map to circuits

共8个练习

3.1.4.1 kmap1

module top_module(
    input a,
    input b,
    input c,
    output out  ); 
    
    assign out = a | b | c;   // 卡诺图化简得到a+b+c
    
endmodule

3.1.4.2 kmap2

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    
    assign out = (~b & ~c) | (~a & ~c & ~d) | (~a & c & ~d) | (~a & b &c) | (b & c & d) | (a & c & d);

endmodule

3.1.4.3 kmap3

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 

    assign out = a | (~a & ~b &c);
endmodule

3.1.4.4 kmap4

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out  ); 
    
    assign out = (a ^ b) ^ (c ^ d);   // 先通过卡诺图写出8个最小项，再进行合并

endmodule

3.1.4.5 Exams/ece241 2013 q2

module top_module (
    input a,
    input b,
    input c,
    input d,
    output out_sop,
    output out_pos
); 

    assign out_sop = c & d | ~a & ~b & c;   // sop：最小项之和，卡诺图圈1
    assign out_pos = c & ~(b & c & ~d) & ~(a & ~b & c);  // pos:最大项之和，卡诺图圈0取反
    
endmodule

3.1.4.6 Exams/m2014 q3

module top_module (
    input [4:1] x, 
    output f );
    
    assign f = ~(~x[1] & ~x[3] | x[1] & x[3] | x[1] & ~x[2]);  // 0少，圈0取反

endmodule

3.1.4.7 Exams/2012 q1g

module top_module (
    input [4:1] x,
    output f
); 
    //assign f = ~x[2] & ~x[4] | ~x[1] & x[3] | x[2] & x[3] & x[4];  // 圈1
    assign f = ~(~x[3] & x[4] | x[2] & ~x[3] | x[1] & x[2] & ~x[4] | x[1] & ~x[2] & x[4]);  // 圈0取反
endmodule

3.1.4.8 Exams/ece241 2014 q3

module top_module (
    input c,
    input d,
    output reg [3:0] mux_in
);
    always @(*)begin
        case({c,d})
            2'b00: mux_in = 4'b0100;
            2'b01: mux_in = 4'b0001;
            2'b10: mux_in = 4'b0101;
            2'b11: mux_in = 4'b1001;
        endcase
    end
endmodule

---

3.2 sequential logic

3.2.1 latches and filp-flops

18个练习

3.2.1.1 dff

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//
	
    always @(posedge clk)   // D触发器为边沿有效
       	q <= d;
endmodule

3.2.1.2 dff8

module top_module (
    input clk,
    input [7:0] d,
    output reg [7:0] q
);
    always @(posedge clk)
        q <= d;    // always块中赋值需为reg类型
endmodule

3.2.1.3 dff8r

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output reg [7:0] q
);
    always @(posedge clk)begin
        if(reset) q <= 0;   // 高电平复位
        else q <= d;
    end
endmodule

3.2.1.4 dff8p

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output reg [7:0] q
);
    always @(negedge clk)begin
        if(reset) q <= 8'h34;
        else q <= d;
    end
endmodule

3.2.1.5 dff8ar

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output reg [7:0] q
);
    always @(posedge clk or posedge areset)begin
        if(areset) q <= 0;
        else q <=d;
    end
endmodule

3.2.1.6 dff16e

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output reg [15:0] q
);
    always @(posedge clk)begin
        if(!resetn)	q <= 0;
        else begin
            if(byteena[0])	q[7:0] <= d[7:0];
            if(byteena[1])  q[15:8] <= d[15:8];
        end
    end
endmodule

3.2.1.7 Exams/m2014 q4a

module top_module (
    input d, 
    input ena,
    output reg q);
    
    always @(*)begin
        if(ena)	q <= d; 
    end
endmodule

3.2.1.8 Exams/m2014 q4b

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output reg q);
    
    always @(posedge clk or posedge ar)begin
        if(ar)	q <= 0;
        else q <= d;
    end
endmodule

3.2.1.9 Exams/m2014 q4c

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
	
    always @(posedge clk)begin
        if(r) q <= 0;
        else q <= d;
    end
endmodule

3.2.1.10 Exams/m2014 q4d

module top_module (
    input clk,
    input in, 
    output out);
    
    wire d;
    assign d = out ^ in;
    always @(posedge clk)
        out <= d;
endmodule

3.2.1.11 Mt2015 muxdff

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    
    wire d;
    assign d = L ? r_in:q_in; 
    always @(posedge clk)
        Q <= d;
endmodule

3.2.1.12 Exams/2014 q4a

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    wire d;
    assign d = L? R: (E?w:Q);
    always @(posedge clk)
        Q <= d;

endmodule

3.2.1.13 Exams/ece241 2014 q4

module top_module (
    input clk,
    input x,
    output z
); 
    wire d1,d2,d3;
    reg  q1,q2,q3;
    assign z = ~(q1 | q2 | q3);
	assign d1 = x ^ q1;
    assign d2 = x & ~q2;
    assign d3 = x | ~q3;
    always @(posedge clk)begin
       	q1 <= d1;
        q2 <= d2;
        q3 <= d3;
    end
endmodule

3.2.1.14 Exams/ece241 2013 q7

module top_module (
    input clk,
    input j,
    input k,
    output reg Q); 
    
    always @(posedge clk)begin
        case({j,k})
            2'b00: Q <= Q;
            2'b01: Q <= 0;
            2'b10: Q <= 1;
            2'b11: Q <= ~Q;   
        endcase
    end
endmodule

3.2.1.15 Edgedetect

module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] pedge
);
    reg [7:0] d;
    always @(posedge clk)begin
		d <= in; 	
        pedge <= ~d & in;
    end
endmodule

3.2.1.16 Edgedetect2

3.2.1.16~3.2.1.18 的解题过程在HDLBits整理3中可以看到

module top_module (
    input clk,
    input [7:0] in,
    output reg [7:0] anyedge
);
    reg [7:0] temp1;
    always @(posedge clk)begin
    	temp1 <= in;
        anyedge <= (in & ~temp1) | (~in & temp1);
    end
endmodule

3.2.1.17 Edgecapture

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output reg [31:0] out
);
    reg [31:0] temp1;
    always @(posedge clk)begin
        temp1 <= in;
        if(reset) out <= 0;
        else out <= out | (~in & temp1); 
    end
endmodule

3.2.1.18 Dualedge

// 方法一，该种方法会出现毛刺，不推荐
module top_module (
    input clk,
    input d,
    output q
);
    reg q1,q2;
    always @(posedge clk)
        q1 <= d;
    always @(negedge clk)
        q2 <= d;
    assign q = clk? q1:q2;

endmodule

// 方法二
module top_module(
	input clk,
	input d,
	output q);
	
	reg p, n;
    always @(posedge clk)
        p <= d ^ n;
    always @(negedge clk)
        n <= d ^ p;
    assign q = p ^ n;
endmodule

3.2.2 Counters

8个练习

3.2.2.1 count15

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output reg [3:0] q);
	
    always @(posedge clk)begin
        if(reset) q <= 0;
        else q <= q+4'd1;
    end
endmodule

3.2.2.2 count10

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output reg [3:0] q);
    
    always @(posedge clk)begin
        if(reset || q == 9) q <= 0;
        else
            q <= q+4'd1;
    end

endmodule

3.2.2.3 coun t1to10

module top_module (
    input clk,
    input reset,
    output reg [3:0] q);
    
    always @(posedge clk)begin
        if(reset || q == 4'd10) q <= 1;
        else q <= q+1;
    end

endmodule

3.2.2.4 Countslow

module top_module (
    input clk,
    input slowena,
    input reset,
    output reg [3:0] q);
    
    always @(posedge clk)begin
        if(reset || (slowena && q == 4'd9)) q <= 0;
        else begin
            if(slowena)	q <= q+1;
        end
    end
endmodule

3.2.2.5 Exams/ece241 2014 q7a

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); //
	assign c_enable = enable;
    assign c_load =   reset | (enable && Q == 4'd12);
    assign c_d    =   c_load;
    
    count4 the_counter (clk, c_enable, c_load, c_d,Q); 
endmodule

3.2.2.6 Exams/ece241 2014 q7b

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
    wire [3:0] q1,q2,q3;
    assign c_enable[0] = 1;
    assign c_enable[1] = (q1 == 4'd9 && c_enable[0])?1:0;
    assign c_enable[2] = (q2 == 4'd9 && c_enable[1])?1:0;
    assign OneHertz    = (q3 == 4'd9 && c_enable[2])?1:0;
    
    bcdcount counter0 (clk, reset, c_enable[0],q1);
    bcdcount counter1 (clk, reset, c_enable[1],q2);
    bcdcount counter2 (clk, reset, c_enable[2],q3);
endmodule

3.2.2.7 Countbcd

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
	
    wire enable;
    assign enable = 1;                     // 个位驱动
    assign ena[1] = (q[3:0] == 4'd9)?1:0;  // 十位驱动
    assign ena[2] = (q[7:4] == 4'd9 && ena[1])?1:0;  // 百位驱动
    assign ena[3] = (q[11:8] == 4'd9 && ena[2] && ena[1])?1:0; // 千位驱动
    bcd q1(clk,reset,enable,q[3:0]);  // 个位  
    bcd q2(clk,reset,ena[1],q[7:4]);
    bcd q3(clk,reset,ena[2],q[11:8]);
    bcd q4(clk,reset,ena[3],q[15:12]);
    
endmodule

module bcd(
	input clk,
    input reset,
    input ena,
    output reg [3:0] out
);
    always @(posedge clk)begin
        if(reset || (out == 9 && ena)) out <= 0;
        else if(ena) out <= out+1;
    end
endmodule

3.2.2.8 Count clock

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output reg [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    wire e_m,e_h;
    reg h_ena;
    tic q1(clk,reset,ena,ss);
    tic q2(clk,reset,e_m,mm);


    assign e_m = (ss == 8'h59 && ena)?1:0;
    assign e_h = (mm == 8'h59 && e_m)?1:0;
    
    always @(posedge clk)begin
        if(reset)begin
            hh <= 8'h12;
            pm <= 0;
        end
        else if(hh == 8'h12 && e_h)		hh <= 1;
        else if(hh[3:0] == 4'h9 && e_h)begin
            hh[3:0] <= 0;
            hh[7:4] <= 1;
        end
        else if(e_h)begin
            hh[3:0] <= hh[3:0] + 1;
            if(hh == 8'h11)	pm <= ~pm;
        end
    end
endmodule

// 60进制模块
module tic(
	input clk,
    input reset,
    input ena,
    output reg [7:0] t_out
);
    wire high;
    assign high = (t_out[3:0]==4'd9 && ena)?1:0;
    
    always @(posedge clk)begin
        if(reset || (t_out[3:0]==4'd9 && ena)) 	t_out[3:0] <= 0;
        else if(ena) 							t_out[3:0] <= t_out[3:0]+1;
    end
    always @(posedge clk)begin
        if(reset || (t_out == 8'h59 && ena))t_out[7:4] <= 0;
        else if(high) 						t_out[7:4] <= t_out[7:4]+1;
    end
    
endmodule

3.2.3 Shift Registers

9个练习

3.2.3.1 Shift4

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    
    always @(posedge clk or posedge areset)begin
        if(areset)	q <= 0;
        else if(load) q <= data;
        else if(ena)  q <= q>>1;
    end

endmodule

3.2.3.2 Rotate100

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
    

    reg [99:0] temp;
    
    always @(posedge clk)begin
        if(load) q <= data;   // load置1时加载数据
    	else begin 
            case(ena)		// 可以直接用if else语句，不用case
                2'b01:  q <= {q[0],q[99:1]};
                2'b10:  q <= {q[98:0],q[99]};
	        	default:q <= q;
        	endcase
        end
    end
endmodule

3.2.3.3 Shift18

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    
    // 逻辑右移时不改变符号位（最高位）
    always @(posedge clk)begin
        if(load) q <= data;
        else if(ena) begin
            case(amount)
                2'b00: q <= {q[62:0],1'b0};
                2'b01: q <= {q[55:0],8'd0};
                2'b10: q <= {q[63],q[63:1]};
                2'b11: q <= {{8{q[63]}},q[63:8]};
            endcase
        end
    end

endmodule

3.2.3.4 Lfsr5

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
    always @(posedge clk)begin
        if(reset) q <= 5'h1;
        else begin
            q[4] <= 0 ^ q[0];
            q[3] <= q[4];
            q[2] <= q[3] ^ q[0];
            q[1] <= q[2];
            q[0] <= q[1];
        end
    end

endmodule

3.2.3.5 Mt2015 lfsr

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
    
    wire [2:0] d;
    assign d = KEY[1]? SW:{LEDR[2] ^ LEDR[1],LEDR[0],LEDR[2]};
    always @(posedge KEY[0])begin
        LEDR <= d;
    end
endmodule

3.2.3.6 Lfsr32

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output reg [31:0] q
); 
    reg [31:0] q_temp;
    always @(*)begin
        q_temp = {1'b0,q[31:1]};
        q_temp[31] = q[0];
        q_temp[21] = q[0] ^ q[22];
        q_temp[1]  = q[0] ^ q[2];
        q_temp[0]  = q[0] ^ q[1];
    end
    always @(posedge clk)begin
        if(reset) q <= 32'h1;
        else	  q <= q_temp;
    end

endmodule

3.2.3.7 Exams/m2014 q4k

// 方法一
module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    
    wire [3:0] b;
    dq q1(clk,resetn,in,b[3]);
    dq q2(clk,resetn,b[3],b[2]);
    dq q3(clk,resetn,b[2],b[1]);
    dq q4(clk,resetn,b[1],out);

endmodule

module dq(
	input clk,
    input reset,
    input in,
    output reg out
);
    always @(posedge clk)begin
        if(~reset)  out <= 0;
        else	out <= in;
    end
endmodule

// 方法二
module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    
    reg [3:0] a;
    always @(posedge clk)begin
        if(~resetn)  a <= 0;
        else	a <= {in,a[3:1]};
    end
    assign out = a[0];
    
endmodule

3.2.3.8 Exams/2014 q4b

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); 
    MUXDFF q[3:0](KEY[0],KEY[1],KEY[2],{KEY[3],LEDR[3:1]},SW,LEDR); 

endmodule

module MUXDFF (
	input clk,
    input E,
    input L,
    input w,
    input R,
    output reg out
);
    always @(posedge clk)begin
        case({E,L})
            2'b00: out <= out;
            2'b01: out <= R;
            2'b10: out <= w;
            2'b11: out <= R;
        endcase
    end
endmodule

3.2.3.9 Exams/ece241 2013 q12

// 方法一
module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    
    // 先创建一个8位的移位寄存器
    reg [7:0] Q;
    always @(*)begin
        case({A,B,C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
        endcase
    end
    always @(posedge clk)begin
        if(enable)
            Q <= {Q[6:0],S};
    end
    
endmodule

// 方法二
module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    
    // 先创建一个8位的移位寄存器
    reg [7:0] Q;
    assign Z = Q[{A,B,C}];
    
    always @(posedge clk)begin
        if(enable)
            Q <= {Q[6:0],S};
    end    
endmodule

3.2.4 More Circuits

3个练习

3.2.4.1 Rule90

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q ); 
    
    always @(posedge clk)begin
        if(load)	q <= data;
        else		q <= {1'b0,q[511:1]} ^ {q[510:0],1'b0};
        
    end

endmodule

3.2.4.2 Rule110

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
    // 通过卡诺图化简
    always @(posedge clk)begin
        if(load)	q <= data;
        else		q <= (~{1'b0,q[511:1]} & {q[510:0],1'b0}) | (q & ~{q[510:0],1'b0}) | (~q & {q[510:0],1'b0});
    end

endmodule

3.2.4.3 Conwaylife