HDLBits之Fsm ps2data

Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).

out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care).

错误代码：

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
    reg [2:0]state,next_state;
    reg [23:0]out_temp;
    parameter S0=3'd0,S1=3'd1,S2=3'd2,S3=3'd3,S4=3'd4;
    
    always@(posedge clk or posedge reset)begin
        if(reset)
           state <= S0;
        else
            state<=next_state;
    end
    always@(*)begin
        case(state)
            S0:next_state=in[3]?S1:S0;
            S1:next_state=S2;
            S2:next_state=S3;
            S3:next_state=in[3]?S1:S0;
        endcase
    end
    always@(*)begin
        case(state)
            S0:out_temp[23:16]=in;
            S1:out_temp[15:8]=in; 此处赋值不合理
            S2:out_temp[7:0]=in;
            S3:out_bytes=out_temp;
        endcase
    end

    // FSM from fsm_ps2

    // New: Datapath to store incoming bytes.

endmodule

out_bytes的输出值不合理。

此处分析是对out的赋值与时钟的关系不合理。

代码：

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //
    reg [2:0]state,next_state;
    reg [23:0]out_temp;
    parameter S0=3'd0,S1=3'd1,S2=3'd2,S3=3'd3,S4=3'd4;
    
    always@(posedge clk or posedge reset)begin
        if(reset)begin
           state <= S0;
            out_temp<=23'd0;
        end
        else begin
            state<=next_state;
            out_temp<={out_temp[15:0],in};
        end
    end
    always@(*)begin
        case(state)
            S0:next_state=in[3]?S1:S0;
            S1:next_state=S2;
            S2:next_state=S3;
            S3:next_state=in[3]?S1:S0;
        endcase
    end
    assign done = (state == S3);
    assign out_bytes = out_temp;
 

    // FSM from fsm_ps2

    // New: Datapath to store incoming bytes.

endmodule