LED:
--********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--********************************************
ENTITY demo2 is
PORT(
K : IN std_logic_vector(7 downto 0);
LED : OUT std_logic_vector(7 downto 0);
ALL_KEY : IN std_logic
);
END demo2;
--*********************************************
ARCHITECTURE behv OF demo2 IS
SIGNAL MY_OUT : std_logic;
BEGIN
PROCESS(K,MY_OUT)
BEGIN
IF MY_OUT='0' THEN
LED <= K;
ELSIF MY_OUT = '1' THEN
LED <= NOT K;
END IF;
END PROCESS;
PROCESS(ALL_KEY)
BEGIN
IF(ALL_KEY'EVENT AND ALL_KEY = '1') THEN
MY_OUT<=NOT MY_OUT;
END IF;
END PROCESS;
end behv;
3-8 1:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demo3 is
PORT (CPS : IN STD_LOGIC_VECTOR( 2 DOWNTO 0) ;
YO : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)) ;
end;
architecture behv1 of demo3 is
BEGIN
WITH not(CPS) SELECT
YO<= "00000001" WHEN "000",
"00000010" WHEN "001",
"00000100" WHEN "010",
"00001000" WHEN "011",
"00010000" WHEN "100",
"00100000" WHEN "101",
"01000000" WHEN "110",
"10000000" WHEN OTHERS ;
end behv1;
3-8 2:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demo3 is
PORT (CPS : IN STD_LOGIC_VECTOR( 2 DOWNTO 0) ;
YO : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)) ;
end;
architecture behv1 of demo3 is
BEGIN
PROCESS(CPS)
BEGIN
CASE CPS IS
WHEN "000"=>YO<="00000001";
WHEN "001"=>YO<="00000010";
WHEN "010"=>YO<="00000100";
WHEN "011"=>YO<="00001000";
WHEN "100"=>YO<="00010000";
WHEN "101"=>YO<="00100000";
WHEN "110"=>YO<="01000000";
WHEN "111"=>YO<="10000000";
WHEN OTHERS=>YO<="11111111";
END CASE;
END PROCESS;
end behv1;
8-3 1:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demo5 is
PORT (CPS : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0) ;
YO : IN STD_LOGIC_VECTOR( 7 DOWNTO 0)) ;
end;
architecture behv1 of demo5 is
BEGIN
PROCESS(YO)
BEGIN
CASE YO IS
WHEN "11111110"=>CPS<="000";
WHEN "11111101"=>CPS<="001";
WHEN "11111011"=>CPS<="010";
WHEN "11110111"=>CPS<="011";
WHEN "11101111"=>CPS<="100";
WHEN "11011111"=>CPS<="101";
WHEN "10111111"=>CPS<="110";
WHEN "01111111"=>CPS<="111";
WHEN OTHERS=>CPS<="111";
END CASE;
END PROCESS;
end behv1;
8-3 2:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demo5 is
PORT (CPS : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0) ;
YO : IN STD_LOGIC_VECTOR( 7 DOWNTO 0)) ;
end;
architecture behv1 of demo5 is
BEGIN
WITH (YO) SELECT
CPS<= "000" WHEN "11111110",
"001" WHEN "11111101",
"010" WHEN "11111011",
"011" WHEN "11110111",
"100" WHEN "11101111",
"101" WHEN "11011111",
"110" WHEN "10111111",
"111" WHEN "01111111",
"111" WHEN OTHERS ;
end behv1;
2位全加器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add2_all is
port(
a,b:in std_logic_vector(1 downto 0); //a,b: 两位的加数引脚
ci:in std_logic; //ci: 进位输入引脚
co:out std_logic; //co: 进位输出引脚
sum:out std_logic_vector(1 downto 0) //sum:和输出引脚
);
end add2_all;
architecture VHDL of add2_all is
signal ci_ns:std_logic; //中间变量
begin
ci_ns <= (a(0) and b(0)) or (b(0) and ci) or (a(0) and ci);
sum(0) <= a(0) xor b(0) xor ci;
co<= (a(1) and b(1)) or (b(1) and ci_ns) or (a(1) and ci_ns);
sum(1) <= a(1) xor b(1) xor ci_ns;
end VHDL;
24进制BCD码计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity BCD is
port(
clk1hz:in std_logic; //时钟计数引脚:上升沿触发计数
en:in std_logic; //使能引脚:高电平有效
low:out std_logic_vector(3 downto 0); //个位:0000(0)~1001(9)
high:out std_logic_vector(3 downto 0) //十位:0000(0)~0010(2)
);
end BCD;
architecture rtl of BCD is
signal low_reg : std_logic_vector(3 downto 0):="0000";
signal high_reg : std_logic_vector(3 downto 0):="0000";
signal clr : std_logic:='0';
begin
low_proc:process(clk1hz, en, clr)
begin
if rising_edge(clk1hz) then
if en = '1' then
if low_reg = "1001" or clr = '1' then
low_reg <= "0000";
else
low_reg <= low_reg + '1';
end if;
end if;
end if;
end process;
low <= low_reg;
high_proc:process(clk1hz, en, clr)
begin
if rising_edge(clk1hz) then
if en = '1' then
if clr = '1' then
high_reg <= "0000";
elsif low_reg = "1001" then
high_reg <= high_reg + '1';
end if;
end if;
end if;
end process;
high <= high_reg;
clr <= '1' when low_reg = "0011" and high_reg = "0010" else '0';
end rtl;