DC综合介绍

DC shell流程介绍：

DC综合shell分析：

set stdlib_path ../../lib
set ss_lib 011N_STD_7T_WORST.db      

set search_path [concat $search_path $stdlib_path]
set target_library [list $ss_lib]
set synthetic_library [list dw_foundation.sldb]
set link_library [list * $ss_lib $synthetic_library]

analyze -format verilog ../../rtl/fifo.v
elaborate fifo
check_design
uniquify

source -echo -verbose ../scr/sdc.tcl
check_timing

compile -map_effort high

report_constraints -all_violators > vio.rpt
report_area -hierarchy > area.rpt
write_file -format verilog -hierarchy -output fifo_syn.v fifo
write_sdc -nosplit sdc_syn.sdc

如上具体不细介绍，另外下面又文本转化介绍

lib转db的步骤
启动library compiler的命令是lc_shell
读入lib库：read_lib xxx.lib
写出db库：write_lib -format db -output xxx.db library_name
注：

library_name可以直接打开lib文件找到，比如：
library(SHM3GTA110_512X60X1CM4b1_ss1p35v125c) {
  date : "2023/04/18 19:16:23";
  revision : 0.2.0;
library_name也可以用list_libs来查询

#!/bin/csh -f


/bin/rm -rf *.vcd *.vec

fsdb2vcd ../../top_tb.fsdb -bt 33500  -et 73100  -o nv2047.vcd                      // 使用vcs命令将fsdb转为vcd文件

#-s /top_tb.u0_NV2047_top.dio1 \
#/top_tb.u0_NV2047_top.dio2\
#/top_tb.u0_NV2047_top.vdd\
#/top_tb.u0_NV2047_top.vdd2\
#/top_tb.u0_NV2047_top.vmid\
#/top_tb.u0_NV2047_top.vss\
#/top_tb.u0_NV2047_top.vss2\
#/top_tb.u0_NV2047_top.SEL_POF\
#/top_tb.u0_NV2047_top.bs\
#/top_tb.u0_NV2047_top.chmod[2]\  
#/top_tb.u0_NV2047_top.chmod[1]\   
#/top_tb.u0_NV2047_top.chmod[0]\   
#/top_tb.u0_NV2047_top.clka\
#/top_tb.u0_NV2047_top.clkb\
#/top_tb.u0_NV2047_top.cs[1]\
#/top_tb.u0_NV2047_top.cs[0]\
#/top_tb.u0_NV2047_top.dinv\
#/top_tb.u0_NV2047_top.dir\
#/top_tb.u0_NV2047_top.dumi[4]\
#/top_tb.u0_NV2047_top.dumi[3]\
#/top_tb.u0_NV2047_top.dumi[2]\
#/top_tb.u0_NV2047_top.dumi[1]\
#/top_tb.u0_NV2047_top.dumi[0]\
#/top_tb.u0_NV2047_top.enable\
#/top_tb.u0_NV2047_top.ld1\
#/top_tb.u0_NV2047_top.ld2\
#/top_tb.u0_NV2047_top.lva[5]\
#/top_tb.u0_NV2047_top.lva[4]\
#/top_tb.u0_NV2047_top.lva[3]\
#/top_tb.u0_NV2047_top.lva[2]\
#/top_tb.u0_NV2047_top.lva[1]\
#/top_tb.u0_NV2047_top.lva[0]\
#/top_tb.u0_NV2047_top.lvb[5]\
#/top_tb.u0_NV2047_top.lvb[4]\
#/top_tb.u0_NV2047_top.lvb[3]\
#/top_tb.u0_NV2047_top.lvb[2]\
#/top_tb.u0_NV2047_top.lvb[1]\
#/top_tb.u0_NV2047_top.lvb[0]\
#/top_tb.u0_NV2047_top.oord\
#/top_tb.u0_NV2047_top.opbias[1]\
#/top_tb.u0_NV2047_top.opbias[0]\
#/top_tb.u0_NV2047_top.pair\
#/top_tb.u0_NV2047_top.pol\
#/top_tb.u0_NV2047_top.sqinv\
#/top_tb.u0_NV2047_top.polc\
#/top_tb.u0_NV2047_top.rpi1\
#/top_tb.u0_NV2047_top.rpi2\
#/top_tb.u0_NV2047_top.rxbias\
#/top_tb.u0_NV2047_top.vgma[18]\
#/top_tb.u0_NV2047_top.vgma[17]\
#/top_tb.u0_NV2047_top.vgma[16]\
#/top_tb.u0_NV2047_top.vgma[15]\
#/top_tb.u0_NV2047_top.vgma[14]\
#/top_tb.u0_NV2047_top.vgma[13]\
#/top_tb.u0_NV2047_top.vgma[12]\
#/top_tb.u0_NV2047_top.vgma[11]\
#/top_tb.u0_NV2047_top.vgma[10]\
#/top_tb.u0_NV2047_top.vgma[9]\
#/top_tb.u0_NV2047_top.vgma[8]\
#/top_tb.u0_NV2047_top.vgma[7]\
#/top_tb.u0_NV2047_top.vgma[6]\
#/top_tb.u0_NV2047_top.vgma[5]\
#/top_tb.u0_NV2047_top.vgma[4]\
#/top_tb.u0_NV2047_top.vgma[3]\
#/top_tb.u0_NV2047_top.vgma[2]\
#/top_tb.u0_NV2047_top.vgma[1]\

#-o nv2047.vcd

vcd2vec -nvcd nv2047.vcd -nsig sig_map -nvec nv2047.vec
vcd2vec -nvcd nv2047.vcd -nsig sig_map_1 -nvec nv2047_1.vec             //vcd 转vec 用于混合仿真的激励

示例项目具体：

set dep [exec depth]
set top nv2049b1n_digital_top
set_svf ${top}.svf

source -echo -verbose $dep/syn/scr/read_lib.tcl
source -echo -verbose $dep/syn/scr/read_rtl.tcl
uniquify

#design rule
source -echo -verbose $dep/syn/scr/design_rule.tcl

set_dont_use {
    M31HSSC900EL150SS_125CSS1P62_cmax_nldm/TIE01X1CS9
    M31HSSC900EL150SS_125CSS1P62_cmax_nldm/TIE0X1CS9
    M31HSSC900EL150SS_125CSS1P62_cmax_nldm/TIE0X4CS9
    M31HSSC900EL150SS_125CSS1P62_cmax_nldm/TIE1X1CS9
    M31HSSC900EL150SS_125CSS1P62_cmax_nldm/TIE1X4CS9
    M31HSSC900EL150SS_N40CFF1P98_cmin_nldm/TIE01X1CS9
    M31HSSC900EL150SS_N40CFF1P98_cmin_nldm/TIE0X1CS9
    M31HSSC900EL150SS_N40CFF1P98_cmin_nldm/TIE0X4CS9
    M31HSSC900EL150SS_N40CFF1P98_cmin_nldm/TIE1X1CS9
    M31HSSC900EL150SS_N40CFF1P98_cmin_nldm/TIE1X4CS9
}

#set dont touch
set_dont_touch {
    u_reg_file/u_buf_i2c_mod_en
    u_data_merge/u_buf_clk_src_inv
}

set_dont_touch {
    u_i2c_slave/u_stop_bit_dly1
}

#remove assign
set verilogout_no_tri true
set_fix_multiple_port_nets \
    -all \
    -feedthroughs \
    -buffer_constants [get_designs]

#timing optimization
source -echo -verbose $dep/syn/scr/mmmc.tcl

#auto insert clock gating
set_clock_gating_style -minimum_bitwidth 1 \
     -positive_edge_logic integrated \
     -negative_edge_logic integrated \
     -control_point before \
     -setup 1 -hold 0

#--------- compile -------------------------------------
set_host_options -max_cores 8
compile_ultra -gate_clock -no_autoungroup

 
check_design > rpt/checkdesign_after_compile.log
report_clock_gating > rpt/auto_clock_gating.rpt

foreach s [all_scenarios] {
    current_scenario $s
    report_constraints -all_violators > rpt/vio_s_${s}.rpt
}

#area optimize
report_area -hierarchy -nosplit > rpt/area_round2.rpt

#-------------- export files ----------------------------------
source -echo -verbose ../scr/rename.tcl

write_file -format ddc -hierarchy -output net/${top}_syn.ddc
write_file -format verilog -hierarchy -output net/${top}_syn.v
 
report_area -physical > rpt/area_physical.log
report_congestion > rpt/congestion.log
report_power > rpt/power.rpt
report_clocks > rpt/clock.rpt
 
foreach s [all_scenarios] {
    current_scenario $s
    write_sdc -nosplit net/sdc_${s}.sdc
}