VHDL读写txt文件

直接上代码模板：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--//TXT相关的Library库
use std.textio.all;
use ieee.std_logic_textio.all;

--//实体
entity wr_txt_tb is
--generic();
--port();
end entity;

--//实体
architecture beha of wr_txt_tb is

--//定义元件及其端口

--//定义常量（时间）
constant PERIOD : time := 5ns;
constant INPUT_FILE  : string:= "data_input.txt";
constant OUTPUT_FILE : string:= "data_output.txt";

--//定义其他信号
signal dv_i     : std_logic:= '0';
signal da_i0    : std_logic_vector(7 downto 0):=(others =>'0');
signal da_i1    : std_logic_vector(7 downto 0):=(others =>'0');
signal da_i2    : std_logic_vector(7 downto 0):=(others =>'0');
signal da_i3    : std_logic_vector(7 downto 0):=(others =>'0');
signal sim_end  : std_logic:= '0';
signal dv_o     : std_logic:= '0';
signal da_o     : std_logic_vector(7 downto 0):=(others =>'0');

signal clk      : std_logic := '0';
signal nRST     : std_logic := '0';
signal RST      : std_logic := '1';
signal cnt      : std_logic_vector(7 downto 0):=(others =>'0');

-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
clk     <= not clk after (PERIOD/2);
nRST    <= '1' after 2*PERIOD;
RST     <= not nRST;
-----------------------------读数据------------------------------
process_read_file : process(clk,nRST)
constant NUM_COL : integer := 4; --number fo column of file
type data_array is array(integer range<>) of std_logic_vector(7 downto 0);
file file_in : text open read_mode is INPUT_FILE;
variable line_in: line;
variable data_in : data_array(1 to NUM_COL); --文件里一行只有多个数（用空格隔开）
-- variable data_in : std_logic_vector(7 downto 0);--文件里一行只有一个数
begin
  if nRST = '0' then

  elsif(rising_edge(clk)) then
    if not(endfile(file_in)) then
        dv_i <= '1';
        readline(file_in, line_in);
        for j in 1 to NUM_COL loop  --一行有多个数，同时读出
            read(line_in, data_in(j));
        end loop;
        da_i0 <= data_in(1);
        da_i1 <= data_in(2);
        da_i2 <= data_in(3);
        da_i3 <= data_in(4);
    else
        dv_i <= '0';
        da_i0 <= (others => '0');
        da_i1 <= (others => '0');
        da_i2 <= (others => '0');
        da_i3 <= (others => '0');
    end if;
  end if;
end process;
---------------------------写数据-----------------------------
process(clk,nRST)begin
    if nRST = '0' then
        cnt <=  (others => '0');
    elsif rising_edge(clk) then
        if cnt(7) = '0' then
            cnt <= cnt + '1';
        end if;

        if cnt(7) = '0' then
            dv_o <= '1';
        else
            dv_o <= '0';
            sim_end <= '1';
        end if;
    end if;
end process;
da_o <= cnt;

process_write_file : process(clk,nRST)
file file_out : text open write_mode is OUTPUT_FILE;
variable line_out:LINE;
begin
  if(nRST = '0') then

  elsif(rising_edge(clk))then
    if(sim_end = '1') then --利用sim_end来控制关闭文件
      file_close(file_out);
    elsif(dv_o='1') then
      write(line_out, da_o, left, 15); --以二进制存储；left表示左对齐，相反，right表示右对齐；15表示字符长度（可用来插入空格）
      -- write(line_out, conv_integer(da_o), left, 15); --以整数存储
      -- hwrite(line_out, da_o, left, 15); --以十六进制存储
      -- hwrite(line_out, x"00"&da_o, left, 15); --以4位十六进制存储
      writeline(file_out,line_out);
      end if;
  end if;
end process;

end beha;