八分频FPGA设计

八分频FPGA Verilog设计

顶层模块

module siv(clk,pwm);
input clk;
output reg pwm;
reg [2:0] c;
always @(posedge clk )
begin
c<=c+1'b1;
pwm = c[2];
end 
endmodule

修改版

module siv(clk,pwm);
input clk;
output reg pwm;
reg [2:0] c=0;

always @(posedge clk )
begin
c<=c+3'b001;
pwm <= c[2];
end 
endmodule

Testbench文档

`timescale 1 ps/ 1 ps
    module siv_vlg_tst();
    // constants                                           
    // general purpose registers
    reg eachvec;
    // test vector input registers
    reg clk;
    // wires                                               
    wire pwm;
    
// assign statements (if any)                          
siv i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.pwm(pwm)
);
initial