「HDLBits题解」Finite State Machines
本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益
题目链接：Fsm1 - HDLBits
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case (state)
A : next_state = in ? A : B ;
B : next_state = in ? B : A ;
default : next_state = B ;
endcase
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if (areset) state <= B ;
else state <= next_state ;
end
// Output logic
assign out = (state == A) ? 0 : 1 ;
endmodule
题目链接：Fsm1s - HDLBits
// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
parameter A = 0, B = 1 ;
reg state, nstate;
always @(posedge clk) begin
if (reset) begin
// Fill in reset logic
state <= B ;
out <= 1 ;
end else begin
case (state)
// Fill in state transition logic
A : nstate = in ? A : B ;
B : nstate = in ? B : A ;
default : nstate = B ;
endcase
// State flip-flops
state <= nstate;
case (nstate)
// Fill in output logic
A : out <= 0 ;
B : out <= 1 ;
default : out <= 1 ;
endcase
end
end
endmodule
题目链接：Fsm2 - HDLBits
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, nstate;
always @(*) begin
// State transition logic
case (state)
ON : nstate = k ? OFF : ON ;
OFF : nstate = j ? ON : OFF ;
default : nstate = OFF ;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= OFF ;
else state <= nstate ;
end
// Output logic
assign out = (state == ON) ? 1 : 0 ;
endmodule
题目链接：Fsm2s - HDLBits
module top_module(
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out);
parameter OFF=0, ON=1;
reg state, nstate;
always @(*) begin
// State transition logic
case (state)
ON : nstate = k ? OFF : ON ;
OFF : nstate = j ? ON : OFF ;
default : nstate = OFF ;
endcase
end
always @(posedge clk) begin
// State flip-flops with synchronous reset
if (reset) state <= OFF ;
else state <= nstate ;
end
// Output logic
assign out = (state == OFF) ? 0 : 1 ;
endmodule
题目链接：Fsm3comb - HDLBits
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: next_state = f(state, in)
always @ (*) begin
case (state)
A : next_state = in ? B : A ;
B : next_state = in ? B : C ;
C : next_state = in ? D : A ;
D : next_state = in ? B : C ;
endcase
end
// Output logic: out = f(state) for a Moore state machine
assign out = (state == D) ? 1 : 0 ;
endmodule
题目链接：Fsm3onehot - HDLBits
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out
);
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = (state[A] & ~in) | (state[C] & ~in) ;
assign next_state[B] = (state[A] & in) | (state[B] & in) | (state[D] & in) ;
assign next_state[C] = (state[B] & ~in) | (state[D] & ~in) ;
assign next_state[D] = (state[C] & in) ;
// Output logic:
assign out = state[D] ;
endmodule
题目链接：Fsm3 - HDLBits
module top_module(
input clk,
input in,
input areset,
output out
);
parameter A = 0, B = 1, C = 2, D = 3 ;
reg [1:0] state, nstate ;
// State transition logic
always @(*) begin
case (state)
A : nstate = in ? B : A ;
B : nstate = in ? B : C ;
C : nstate = in ? D : A ;
D : nstate = in ? B : C ;
default : nstate = A ;
endcase
end
// State flip-flops with asynchronous reset
always @(posedge clk or posedge areset) begin
if (areset) state <= A ;
else state <= nstate ;
end
// Output logic
assign out = state == D ;
endmodule
题目链接：Fsm3s - HDLBits
module top_module(
input clk,
input in,
input reset,
output out
);
parameter A = 0, B = 1, C = 2, D = 3 ;
reg [1:0] state, nstate ;
// State transition logic
always @(*) begin
case (state)
A : nstate = in ? B : A ;
B : nstate = in ? B : C ;
C : nstate = in ? D : A ;
D : nstate = in ? B : C ;
default : nstate = A ;
endcase
end
// State flip-flops with asynchronous reset
always @(posedge clk) begin
if (reset) state <= A ;
else state <= nstate ;
end
// Output logic
assign out = state == D ;
endmodule
题目链接：Exams/ece241 2013 q4 - HDLBits
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter [2:0] A = 3'd0, //below s1
B0 = 3'd1, //s1~s2, and previous level is higher
B1 = 3'd2, //s1~s2, and previous level is lower
C0 = 3'd3, //s2~s3, and previous level is higher
C1 = 3'd4, //s2~s3, and previous level is lower
D = 3'd5; //above s3
reg [2:0] state, nstate ;
always @(posedge clk) begin
if (reset) state <= A ;
else state <= nstate ;
end
always @ (*) begin
case (state)
A : nstate = s[1] ? B1 : A ;
B0 : nstate = s[2] ? C1 : s[1] ? B0 : A ;
B1 : nstate = s[2] ? C1 : s[1] ? B1 : A ;
C0 : nstate = s[3] ? D : s[2] ? C0 : B0 ;
C1 : nstate = s[3] ? D : s[2] ? C1 : B0 ;
D : nstate = s[3] ? D : C0 ;
default :nstate = 3'bxxx ;
endcase
end
always @(*) begin
case (state)
A : {fr3, fr2, fr1, dfr} = 4'b1111 ;
B0 : {fr3, fr2, fr1, dfr} = 4'b0111 ;
B1 : {fr3, fr2, fr1, dfr} = 4'b0110 ;
C0 : {fr3, fr2, fr1, dfr} = 4'b0011 ;
C1 : {fr3, fr2, fr1, dfr} = 4'b0010 ;
D : {fr3, fr2, fr1, dfr} = 4'b0000 ;
default : {fr3, fr2, fr1, dfr} = 4'bxxxx ;
endcase
end
endmodule题目链接：Lemmings1 - HDLBits
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right); //
parameter LEFT=0, RIGHT=1 ;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
LEFT : next_state = bump_left ? RIGHT : LEFT ;
RIGHT : next_state = bump_right ? LEFT : RIGHT ;
default : next_state = LEFT ;
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if (areset) state <= LEFT ;
else state <= next_state ;
end
// Output logic
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
endmodule
题目链接：Lemmings2 - HDLBits
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter LEFT = 0, RIGHT = 1, FALL_L = 2, FALL_R = 3 ;
reg [1:0] state, nstate ;
always @(*) begin
case (state)
LEFT : nstate = !ground ? FALL_L : bump_left ? RIGHT : LEFT ;
RIGHT : nstate = !ground ? FALL_R : bump_right ? LEFT : RIGHT ;
FALL_L : nstate = ground ? LEFT : FALL_L ;
FALL_R : nstate = ground ? RIGHT : FALL_R ;
default : nstate = LEFT ;
endcase
end
always @(posedge clk or posedge areset) begin
if (areset) state <= LEFT ;
else state <= nstate ;
end
assign walk_left = state == LEFT ;
assign walk_right = state == RIGHT ;
assign aaah = state == FALL_L | state == FALL_R ;
endmodule
题目链接：Lemmings3 - HDLBits
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 0, RIGHT = 1, DIG_L = 2, DIG_R = 3, FALL_L = 4, FALL_R = 5 ;
reg [2:0] state, nstate ;
always @ (posedge clk or posedge areset) begin
if (areset) state <= LEFT ;
else state <= nstate ;
end
assign {walk_left, walk_right, aaah, digging} = {state == LEFT, state == RIGHT, state == FALL_L | state == FALL_R, state == DIG_L | state == DIG_R} ;
always @ (*) begin
case (state)
LEFT : nstate = !ground ? FALL_L : dig ? DIG_L : bump_left ? RIGHT : LEFT ;
RIGHT : nstate = !ground ? FALL_R : dig ? DIG_R : bump_right ? LEFT : RIGHT ;
DIG_L : nstate = !ground ? FALL_L : DIG_L ;
DIG_R : nstate = !ground ? FALL_R : DIG_R ;
FALL_L : nstate = ground ? LEFT : FALL_L ;
FALL_R : nstate = ground ? RIGHT : FALL_R ;
default : nstate = LEFT ;
endcase
end
endmodule
题目链接：Lemmings4 - HDLBits
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 0, RIGHT = 1, DIG_L = 2, DIG_R = 3, FALL_L = 4, FALL_R = 5, SPLAT = 6 ;
reg [2:0] state, nstate ;
reg [6:0] cnt ;
always @ (posedge clk or posedge areset) begin
if (areset) cnt <= 0 ;
else if (state == FALL_L || state == FALL_R) cnt <= cnt + 1 ;
else cnt <= 0 ;
end
always @ (posedge clk or posedge areset) begin
if (areset) state <= LEFT ;
else state <= nstate ;
end
assign {walk_left, walk_right, aaah, digging} = {state == LEFT, state == RIGHT, state == FALL_L || state == FALL_R, state == DIG_L || state == DIG_R} ;
always @ (*) begin
case (state)
LEFT : nstate = !ground ? FALL_L : dig ? DIG_L : bump_left ? RIGHT : LEFT ;
RIGHT : nstate = !ground ? FALL_R : dig ? DIG_R : bump_right ? LEFT : RIGHT ;
DIG_L : nstate = !ground ? FALL_L : DIG_L ;
DIG_R : nstate = !ground ? FALL_R : DIG_R ;
FALL_L : begin
if (ground) begin
if (cnt > 19) nstate = SPLAT ;
else nstate = LEFT ;
end
else nstate = FALL_L ;
end
FALL_R : begin
if (ground) begin
if (cnt > 19) nstate = SPLAT ;
else nstate = RIGHT ;
end
else nstate = FALL_R ;
end
SPLAT : nstate = SPLAT ;
default : nstate = LEFT ;
endcase
end
endmodule
题目链接：Fsm onehot - HDLBits
module top_module(
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6, S7 = 7, S8 = 8, S9 = 9 ;
// state
assign next_state[S0] = (state[S0] & !in) | (state[S1] & !in) | (state[S2] & !in) | (state[S3] & !in) | (state[S4] & !in) |
(state[S7] & !in) | (state[S8] & !in) | (state[S9] & !in) ;
assign next_state[S1] = (state[S0] & in) | (state[S8] & in) | (state[S9] & in) ;
assign next_state[S2] = state[S1] & in ;
assign next_state[S3] = state[S2] & in ;
assign next_state[S4] = state[S3] & in ;
assign next_state[S5] = state[S4] & in ;
assign next_state[S6] = state[S5] & in ;
assign next_state[S7] = (state[S6] & in) | (state[S7] & in) ;
assign next_state[S8] = state[S5] & !in ;
assign next_state[S9] = state[S6] & !in ;
//out
assign out1 = state[S8] | state[S9] ;
assign out2 = state[S7] | state[S9] ;
endmodule
题目链接：Fsm ps2 - HDLBits
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
);
wire x ;
assign x = in[3] ;
parameter idle = 0, S1 = 1, S2 = 2, S3 = 3 ;
reg [1:0] state, nstate ;
// State transition logic (combinational)
always @ (*) begin
case (state)
idle : nstate = x ? S1 : idle ;
S1 : nstate = S2 ;
S2 : nstate = S3 ;
S3 : nstate = x ? S1 : idle ;
default : nstate = idle ;
endcase
end
// State flip-flops (sequential)
always @(posedge clk) begin
if (reset) state <= idle ;
else state <= nstate ;
end
// Output logic
assign done = (state == S3) ;
endmodule
题目链接：Fsm ps2data - HDLBits
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done
);
wire x ;
assign x = in[3] ;
parameter idle = 0, S1 = 1, S2 = 2, S3 = 3 ;
reg [1:0] state, nstate ;
reg [23:0] data ;
// State transition logic (combinational)
always @ (*) begin
case (state)
idle : nstate = x ? S1 : idle ;
S1 : nstate = S2 ;
S2 : nstate = S3 ;
S3 : nstate = x ? S1 : idle ;
default : nstate = idle ;
endcase
end
// State flip-flops (sequential)
always @(posedge clk) begin
if (reset) begin
state <= idle ;
data <= 24'b0 ;
end
else begin
state <= nstate ;
data <= {data[15:0], in} ;
end
end
// Output logic
assign done = (state == S3) ;
assign out_bytes = done ? data : 24'b0 ;
endmodule
题目链接：Fsm serial - HDLBits
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter IDLE = 0, START = 1, RECEIVE = 2, WAIT = 3, STOP = 4 ;
reg [2:0] nstate, state ;
reg [3:0] i ;
always @(posedge clk) begin
if (reset) state <= IDLE ;
else state <= nstate ;
end
always @ (*) begin
case (state)
IDLE : nstate = in ? IDLE : START ;
START : nstate = RECEIVE ;
RECEIVE : nstate = i == 8 ? (in ? STOP : WAIT) : RECEIVE ;
WAIT : nstate = in ? IDLE : WAIT ;
STOP : nstate = in ? IDLE : START ;
endcase
end
always @ (posedge clk) begin
if (reset) begin
done <= 0 ;
i <= 0 ;
end
else
case (nstate)
RECEIVE : begin
done <= 0 ;
i <= i + 1 ;
end
STOP : begin
done <= 1 ;
i <= 0 ;
end
default : begin
done <= 0 ;
i <= 0 ;
end
endcase
end
endmodule
题目链接：Fsm serialdata - HDLBits
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
);
parameter IDLE = 0, START = 1, RECEIVE = 2, WAIT = 3, STOP = 4 ;
reg [2:0] nstate, state ;
reg [3:0] i ;
reg [7:0] data ;
assign out_byte = (state == STOP) ? data : 0 ;
always @(posedge clk) begin
if (reset) state <= IDLE ;
else state <= nstate ;
end
always @(posedge clk) begin
if (reset) data <= 0 ;
else if (state == STOP) data <= 0 ;
else if (nstate == STOP) data <= data ;
else data <= {in, data[7:1]} ;
end
always @ (*) begin
case (state)
IDLE : nstate = in ? IDLE : START ;
START : nstate = RECEIVE ;
RECEIVE : nstate = i == 8 ? (in ? STOP : WAIT) : RECEIVE ;
WAIT : nstate = in ? IDLE : WAIT ;
STOP : nstate = in ? IDLE : START ;
endcase
end
always @ (posedge clk) begin
if (reset) begin
done <= 0 ;
i <= 0 ;
end
else
case (nstate)
RECEIVE : begin
done <= 0 ;
i <= i + 1 ;
end
STOP : begin
done <= 1 ;
i <= 0 ;
end
default : begin
done <= 0 ;
i <= 0 ;
end
endcase
end
endmodule
题目链接：Fsm serialdp - HDLBits
module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
);
parameter IDLE = 0, START = 1, RECEIVE = 2, WAIT = 3, STOP = 4, CHECK = 5 ;
reg [2:0] nstate, state ;
reg [3:0] i ;
reg [7:0] data ;
reg odd_reset;
reg odd_reg;
wire odd ;
always @(posedge clk) begin
if (reset) state <= IDLE ;
else state <= nstate ;
end
always @(posedge clk) begin
if (reset) data <= 0 ;
else if (nstate == RECEIVE) data[i] <= in ;
end
always @ (*) begin
case (state)
IDLE : nstate = in ? IDLE : START ;
START : nstate = RECEIVE ;
RECEIVE : nstate = i == 8 ? CHECK : RECEIVE ;
CHECK : nstate = in ? STOP : WAIT ;
WAIT : nstate = in ? IDLE : WAIT ;
STOP : nstate = in ? IDLE : START ;
endcase
end
always @ (posedge clk) begin
if (reset) i <= 0 ;
else
case (nstate)
RECEIVE : i = i + 1 ;
STOP : i <= 0 ;
default : i <= 0 ;
endcase
end
parity u_parity(
.clk(clk),
.reset(reset | odd_reset),
.in(in),
.odd(odd));
always @(posedge clk) begin
if(reset) odd_reg <= 0;
else odd_reg <= odd;
end
always @(posedge clk) begin
case(nstate)
IDLE : odd_reset <= 1;
STOP : odd_reset <= 1;
default : odd_reset <= 0;
endcase
end
assign done = ((state == STOP) && odd_reg);
assign out_byte = (done) ? data : 8'b0;
endmodule
题目链接：Fsm hdlc - HDLBits
module top_module(
input clk,
input reset, // Synchronous reset
input in,
output disc, // 0111110
output flag, // 01111110
output err // 01111111...
);
parameter idle = 0, // 0
S1 = 1, // 01
S2 = 2, // 011
S3 = 3, // 0111
S4 = 4, // 01111
S5 = 5, // 011111
S6 = 6, // 0111110
S7 = 7, // 0111111
S8 = 8, // 01111110
S9 = 9 ; // 01111111
reg [3:0] nstate, state ;
always @ (posedge clk) begin
if (reset) state <= idle ;
else state <= nstate ;
end
always @ (*) begin
case (state)
idle : nstate = in ? S1 : idle ;
S1 : nstate = in ? S2 : idle ;
S2 : nstate = in ? S3 : idle ;
S3 : nstate = in ? S4 : idle ;
S4 : nstate = in ? S5 : idle ;
S5 : nstate = in ? S7 : S6 ;
S6 : nstate = in ? S1 : idle ;
S7 : nstate = in ? S9 : S8 ;
S8 : nstate = in ? S1 : idle ;
S9 : nstate = in ? S9 : idle ;
default : nstate = idle ;
endcase
end
assign disc = state == S6 ;
assign flag = state == S8 ;
assign err = state == S9 ;
endmodule
题目链接：Exams/ece241 2013 q8 - HDLBits
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z // 101 include Overlap
);
parameter idle = 0, // 0
S1 = 1, // 1
S2 = 2 ; // 10
reg [1:0] state, nstate ;
always @(posedge clk or negedge aresetn) begin
if (!aresetn) state <= idle ;
else state <= nstate ;
end
always @ (*) begin
case (state)
idle : nstate = x ? S1 : idle ;
S1 : nstate = x ? S1 : S2 ;
S2 : nstate = x ? S1 : idle ;
default : nstate = idle ;
endcase
end
assign z = (state == S2 && x) ;
endmodule
题目链接：Exams/ece241 2014 q5a - HDLBits
module top_module (
input clk,
input areset,
input x,
output z
);
parameter A = 0, B = 1, C = 2 ;
reg [1:0] state, nstate ;
always @(*) begin
case (state)
A : nstate = x ? B : A ;
B : nstate = x ? C : B ;
C : nstate = x ? C : B ;
default : nstate = A ;
endcase
end
always @ (posedge clk or posedge areset) begin
if (areset) state <= A ;
else state <= nstate ;
end
assign z = state == B;
endmodule题目链接：Exams/ece241 2014 q5b - HDLBits
module top_module (
input clk,
input areset,
input x,
output z
);
parameter A = 0, B = 1 ;
reg state, nstate ;
always @(*) begin
case (state)
A : nstate = x ? B : A ;
B : nstate = B ;
default : nstate = A ;
endcase
end
always @ (posedge clk or posedge areset) begin
if (areset) state <= A ;
else state <= nstate ;
end
assign z = (state == A & x) | (state == B & !x) ;
endmodule题目链接：Exams/2014 q3fsm - HDLBits
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter A = 0, B = 1 ;
reg state, nstate ;
reg [2:0] cntw ;
reg [1:0] cntn ;
always @(posedge clk) begin
if (reset) state <= A ;
else state <= nstate ;
end
always @ (*) begin
case (state)
A : nstate = s ? B : A ;
B : nstate = B ;
default : nstate = A ;
endcase
end
always @ (posedge clk) begin
if (reset) cntw <= 0 ;
else if (state == B) cntw <= {cntw[1:0], w} ;
end
always @ (posedge clk) begin
if (reset) cntn <= 0 ;
else if (nstate == B) cntn <= cntn == 3 ? 1 : cntn + 1 ;
end
assign z = (cntn == 1 && (cntw == 3'b110 || cntw == 3'b101 || cntw == 3'b011)) ;
endmodule
题目链接：Exams/2014 q3bfsm - HDLBits
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4 ;
reg [2:0] state, nstate ;
always @(posedge clk) begin
if (reset) state <= S0 ;
else state <= nstate ;
end
always @(*) begin
case (state)
S0 : nstate = x ? S1 : S0 ;
S1 : nstate = x ? S4 : S1 ;
S2 : nstate = x ? S1 : S2 ;
S3 : nstate = x ? S2 : S1 ;
S4 : nstate = x ? S4 : S3 ;
default : nstate = S0 ;
endcase
end
assign z = (state == S3 || state == S4) ;
endmodule
题目链接：Exams/2014 q3c - HDLBits
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
reg [2:0] Y ;
always @(*) begin
case (y)
3'b000 : Y <= x ? 3'b001 : 3'b000 ;
3'b001 : Y <= x ? 3'b100 : 3'b001 ;
3'b010 : Y <= x ? 3'b001 : 3'b010 ;
3'b011 : Y <= x ? 3'b010 : 3'b001 ;
3'b100 : Y <= x ? 3'b100 : 3'b011 ;
endcase
end
assign Y0 = Y[0] ;
assign z = (y == 3'b011 || y == 3'b100) ;
endmodule 题目链接：Exams/m2014 q6b - HDLBits
module top_module (
input [3:1] y,
input w,
output Y2
);
reg [3:1] Y ;
assign Y2 = Y[2] ;
always @(*) begin
case (y)
3'b000 : Y = w ? 3'b001 : 3'b000 ;
3'b001 : Y = w ? 3'b011 : 3'b010 ;
3'b010 : Y = w ? 3'b011 : 3'b100 ;
3'b011 : Y = w ? 3'b000 : 3'b101 ;
3'b100 : Y = w ? 3'b011 : 3'b100 ;
3'b101 : Y = w ? 3'b011 : 3'b010 ;
endcase
end
endmodule
题目链接：Exams/m2014 q6c - HDLBits
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1] & ~w ;
assign Y4 = (y[2] & w) | (y[3] & w) | (y[5] & w) | (y[6] & w) ;
endmodule
题目链接：Exams/m2014 q6 - HDLBits
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100, f = 3'b101 ;
reg [2:0] state, nstate ;
always @(*) begin
case ({state, w})
{a, 1'b0} : nstate = b ;
{a, 1'b1}: nstate = a;
{b, 1'b0}: nstate = c;
{b, 1'b1}: nstate = d;
{c, 1'b0}: nstate = e;
{c, 1'b1}: nstate = d;
{d, 1'b0}: nstate = f;
{d, 1'b1}: nstate = a;
{e, 1'b0}: nstate = e;
{e, 1'b1}: nstate = d;
{f, 1'b0}: nstate = c;
{f, 1'b1}: nstate = d;
default : nstate = a;
endcase
end
always @(posedge clk) begin
if (reset) state <= a ;
else state <= nstate ;
end
assign z = (state == e) | (state == f) ;
endmodule
题目链接：Exams/2012 q2fsm - HDLBits
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100, f = 3'b101 ;
reg [2:0] state, nstate ;
always @(*) begin
case ({state, w})
{a, 1'b0} : nstate = a ;
{a, 1'b1}: nstate = b;
{b, 1'b0}: nstate = d;
{b, 1'b1}: nstate = c;
{c, 1'b0}: nstate = d;
{c, 1'b1}: nstate = e;
{d, 1'b0}: nstate = a;
{d, 1'b1}: nstate = f;
{e, 1'b0}: nstate = d;
{e, 1'b1}: nstate = e;
{f, 1'b0}: nstate = d;
{f, 1'b1}: nstate = c;
default : nstate = a;
endcase
end
always @(posedge clk) begin
if (reset) state <= a ;
else state <= nstate ;
end
assign z = (state == e) | (state == f) ;
endmodule
题目链接：Exams/2012 q2b - HDLBits
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = (y[0] && w) ;
assign Y3 = (y[1] && ~w) | (y[2] && ~w) | (y[4] && ~w) | (y[5] && ~w) ;
endmodule
题目链接：Exams/2013 q2afsm - HDLBits
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
parameter A = 0, B = 1, C = 2, D = 3 ;
reg [1:0] state, nstate ;
always @ (posedge clk) begin
if (!resetn) state <= A ;
else state <= nstate ;
end
always @ (*) begin
case (state)
A : nstate = r[1] ? B : r[2] ? C : r[3] ? D : A ;
B : nstate = r[1] ? B : A ;
C : nstate = r[2] ? C : A ;
D : nstate = r[3] ? D : A ;
endcase
end
assign g[1] = state == B ;
assign g[2] = state == C ;
assign g[3] = state == D ;
endmodule
题目链接：Exams/2013 q2bfsm - HDLBits
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output f,
output g
);
parameter A = 0, f1 = 1, tmp0 = 2, tmp1 = 3, tmp2 = 4, g1 = 5, g1p = 6, tmp3 = 7, g0p = 8 ;
reg [3:0] state, nstate ;
always @(*) begin
case (state)
A : nstate = resetn ? f1 : A ;
f1 : nstate = tmp0 ;
tmp0 : nstate = x ? tmp1 : tmp0 ;
tmp1 : nstate = ~x ? tmp2 : tmp1 ;
tmp2 : nstate = x ? g1 : tmp0 ;
g1 : nstate = y ? g1p : tmp3 ;
tmp3 : nstate = y ? g1p : g0p ;
g1p : nstate = ~resetn ? A : g1p ;
g0p : nstate = ~resetn ? A : g0p ;
endcase
end
always @(posedge clk) begin
if (~resetn) state <= A ;
else state <= nstate ;
end
always @ (posedge clk) begin
case (nstate)
f1 : f <= 1 ;
g1 : g <= 1 ;
tmp3 : g <= 1 ;
g1p : g <= 1 ;
g0p : g <= 0 ;
default : begin
f <= 0 ;
g <= 0 ;
end
endcase
end
endmodule