dram的刷新详解

In typical modern DRAM systems, thememory controller periodically issues anauto-refresh (auto-refreshis sometimes called CAS-before-RAS refresh)command to the DRAM.The DRAM chip thenchooses which rows to refresh using an internal counter, and refreshes a numberof rows based on the device capacity. During normal temperature operation (below 85’C), the average time between auto-refresh commands(called tREFI ) is 7.8us . In the extended temperature range (between 85 _C and 95 _C), the temperature range in whichdense server environments operate [10] and 3D-stacked DRAMs are expected tooperate [1], the time between

auto-refresh commands is halved to 3.9 us [15]. An auto-refresh operation occupies all banks on the ranksimultaneously (preventing the rank from servicing any requests) for a lengthof time tRFC, where tRFC depends on the number of rows beingrefreshed.

  Previous DRAM generationsalso allowed the memory controller to perform refreshes byopening rows one-by-one (calledRAS-only refresh [30]), butthismethod has been deprecated due to the additional powerrequired to send row addresses on the bus.

Some devices support per-bank refreshcommands, which refresh several rows at a single bank [16], allowing forbank-level parallelism at a rank during refreshes. However, this feature is notavailable in most DRAM devices.

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JEDEC standards [1] specify that DRAM devices must be refreshed every 64 millisecond (32 millisecond at above 85‘C temperature). All the DRAM rows must undergo refresh within this time period. The total time incurred in doing refresh is thus proportional to the number of rows in memory, and approximately doubles as the number of rows in the DRAM array is doubled. Initial DRAM designs performed Burst Refreshes whereby refresh for all DRAM rows happened in succession; however, this mode makes memory unavailable for a long periods of time. To avoid this long latency,JEDEC standards support Distributed Refresh mode. In this mode, the total number of rows in a bank is divided into 8K groups, and each group is refreshed within a time period equal to 7.8 μsecond (3.9 μsecond at high temperatures). This time duration is referred to as Refresh Interval or TREFI . The DRAM controller sends a refresh pulse to DRAM devices once every TREFI . The standard for TREFI was developed when memory banks typically had 8K rows; therefore each refresh pulse refreshed exactly one row. Over time, as the size of memory has increased, the TREFI has remained the same, only the number of rows refreshed per refresh pulse has increased.
For example, for the 8Gb DRAM chips we consider, each refresh pulse refreshes 8-16 rows. Therefore, the latency
to do refresh for one group is almost an order of magnitude longer than a typical read operation.

在典型的现代dram系统中，MC周期性的向dram发送auto-refresh(有时候这这种刷新方式称为CAS-before-RAS刷新)命令。Dram芯片使用一个内部计数器，来选择需要刷新哪些行，每一次刷新的行数和Dram的容量有关。在正常温度下(低于85‘C)，auto-refresh命令的时间间隔(称为tREFI)为7.8us，在高温下(介于85’C和95‘C，通常密集的服务器环境和3D dram处于这种温度下)，时间间隔为3.9us.一个auto-refresh操作同时占有一个rank的所有的bank(使rank不能相应任何内存请求)的时间为tRFC(注意：tRFC为刷新所占用的时间，而tREFI为两次刷新的时间间隔)，而tRFC取决于刷新的行数。（注：这种方式最为常见）

         以前的Dram也允许MC通过一行一行的打开每一行的方式执行刷新操作(称为RAS-only刷新)，但是由于需要额外的功耗来向总线传送行地址，所以这种方式被废弃了。

         有的Dram也支持每个bank刷新的命令，每次同时刷新一个bank的多个行，在一个rank刷新的时候允许bank-level 并行(注：这指的是刷新rank中的一个bank的时候，可以访问这个rank的另外一个bank)。

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JEDEC(联合电子设备工程会议 Joint Electron Device Engineering Council ) 规定必须在64ms内对每一行至少刷新一次，刷新所占的时间与内存中的行数成比例，如果dram中的行数加倍的话，那么刷新所占的时间也大约提高一倍，有集中式刷新(Burst Refresh)和分布式刷新(Distributed Refresh)。为了避免过长的"死时间"，JEDEC也支持分布式刷新，在这种刷新模式下，一个bank中的所有row被分成一些具有8K个row的组，每个组在7.8us(高温情况下，没隔3.9us刷新一次)会被刷新一次。7.8us(或者3.9us

这个tREFI)是在每个bank有8K个行（即 64ms = 7.8us × 8 × 1024）时提出来的，这是基本上就是每个刷新脉冲刷新一个行。但是，随着dram容量的增加，tREFI保持不变，但是每个刷新脉冲需要刷新的行数增加。比如说，对于8Gb的dram，每个刷新脉冲需要刷新8-16个行。因此，每个tREFI时间内，花在刷新的时间大概是一次读操作所花时间的10倍左右（这是因为，刷新一行的时间和一次读操作的时间相同）。

参考资料：

RAIDR: Retention-Aware Intelligent DRAM Refresh,Jamie Liu Ben Jaiyen Richard Veras Onur Mutlu
Carnegie Mellon University
{jamiel,bjaiyen,rveras,onur}@cmu.edu

A Case for Refresh Pausing in DRAM Memory Systems
Prashant Nair Chia-Chen Chou Moinuddin K. Qureshi
School of Electrical and Computer Engineering Georgia Institute of Technology
{pnair6, cchou34, moin}@gatech.edu