EZ430 chronos 套件源码集合II(7个ADC12,5个COMP_B)
ADC12;
cc430x613x_adc12_01.c ADC12, Sample A0, Set P1.0 if A0 > 0.5*AVcc
//****************************************************************************** // C430F613x Demo - ADC12_A, Sample A0, Set P1.0 if A0 > 0.5*AVcc // // Description: A single sample is made on A0 with reference to AVcc. // Software sets ADC12SC to start sample and conversion - ADC12SC // automatically cleared at EOC. ADC12 internal oscillator times sample (16x) // and conversion. In mainloop CC430 waits in LPM0 to save power until ADC12 // conversion complete, ADC12_ISR will force exit from LPM0 in Mainloop on // reti. If A0 > 0.5*AVcc, P1.0 set, else reset. // // CC430F6137 // ----------------- // /|\| | // | | | // --|RST | // | | // Vin -->|P2.0/A0 P1.0|--> LED // // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.2 //****************************************************************************** #include "cc430x613x.h" void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT ADC12CTL0 = ADC12SHT02 + ADC12ON; // Sampling time, ADC12 on ADC12CTL1 = ADC12SHP; // Use sampling timer ADC12IE = 0x01; // Enable interrupt ADC12CTL0 |= ADC12ENC; P2SEL |= BIT0; // P2.0 ADC option select P1DIR |= BIT0; // P1.0 output while (1) { ADC12CTL0 |= ADC12SC; // Start sampling/conversion __bis_SR_register(LPM0_bits + GIE); // LPM0, ADC12_ISR will force exit __no_operation(); // For debugger } } #pragma vector = ADC12_VECTOR __interrupt void ADC12_ISR(void) { switch(__even_in_range(ADC12IV,34)) { case 0: break; // Vector 0: No interrupt case 2: break; // Vector 2: ADC overflow case 4: break; // Vector 4: ADC timing overflow case 6: // Vector 6: ADC12IFG0 if (ADC12MEM0 >= 0x7ff) // ADC12MEM = A0 > 0.5AVcc? P1OUT |= BIT0; // P1.0 = 1 else P1OUT &= ~BIT0; // P1.0 = 0 __bic_SR_register_on_exit(LPM0_bits); // Exit active CPU case 8: break; // Vector 8: ADC12IFG1 case 10: break; // Vector 10: ADC12IFG2 case 12: break; // Vector 12: ADC12IFG3 case 14: break; // Vector 14: ADC12IFG4 case 16: break; // Vector 16: ADC12IFG5 case 18: break; // Vector 18: ADC12IFG6 case 20: break; // Vector 20: ADC12IFG7 case 22: break; // Vector 22: ADC12IFG8 case 24: break; // Vector 24: ADC12IFG9 case 26: break; // Vector 26: ADC12IFG10 case 28: break; // Vector 28: ADC12IFG11 case 30: break; // Vector 30: ADC12IFG12 case 32: break; // Vector 32: ADC12IFG13 case 34: break; // Vector 34: ADC12IFG14 default: break; } }
cc430x613x_adc12_02.c ADC12, Using the Internal Reference
//****************************************************************************** // CC430F613x Demo - ADC12_A, Using the Internal Reference // // Description: This example shows how to use the shared reference for ADC12 // sampling and performs a single conversion on channel A0. The conversion // results are stored in ADC12MEM0. Test by applying a voltage to channel A0, // then setting and running to a break point at the "__no_operation()" // instruction. To view the conversion results, open an ADC12 register window // in debugger and view the contents of ADC12MEM0 // // CC430F613x // ----------------- // /|\| | // | | | // --|RST | // | | // Vin -->|P2.0/A0 | // | | // // M. Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" void main(void) { WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer P2SEL |= BIT0; // Enable A/D channel A0 /* Initialize REF module */ // Enable 2.5V shared reference, disable temperature sensor to save power REFCTL0 |= REFMSTR+REFVSEL_2+REFON+REFTCOFF; /* Initialize ADC12 */ ADC12CTL0 = ADC12ON+ADC12SHT02; // Turn on ADC12, set sampling time ADC12CTL1 = ADC12SHP; // Use sampling timer ADC12MCTL0 = ADC12SREF_1; // Vr+=Vref+ and Vr-=AVss __delay_cycles(75); // 75 us delay @ ~1MHz ADC12CTL0 |= ADC12ENC; // Enable conversions while (1) { ADC12CTL0 |= ADC12SC; // Start conversion while (!(ADC12IFG & BIT0)); __no_operation(); // SET BREAKPOINT HERE } }
cc430x613x_adc12_05.c ADC12, Using an External Reference
//****************************************************************************** // CC430F613x Demo - ADC12_A, Using the Internal Reference // // Description: This example shows how to use the shared reference for ADC12 // sampling and performs a single conversion on channel A0. The conversion // results are stored in ADC12MEM0. Test by applying a voltage to channel A0, // then setting and running to a break point at the "__no_operation()" // instruction. To view the conversion results, open an ADC12 register window // in debugger and view the contents of ADC12MEM0 // // CC430F613x // ----------------- // /|\| | // | | | // --|RST | // | | // Vin -->|P2.0/A0 | // | | // // M. Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" void main(void) { WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer P2SEL |= BIT0; // Enable A/D channel A0 /* Initialize REF module */ // Enable 2.5V shared reference, disable temperature sensor to save power REFCTL0 |= REFMSTR+REFVSEL_2+REFON+REFTCOFF; /* Initialize ADC12 */ ADC12CTL0 = ADC12ON+ADC12SHT02; // Turn on ADC12, set sampling time ADC12CTL1 = ADC12SHP; // Use sampling timer ADC12MCTL0 = ADC12SREF_1; // Vr+=Vref+ and Vr-=AVss __delay_cycles(75); // 75 us delay @ ~1MHz ADC12CTL0 |= ADC12ENC; // Enable conversions while (1) { ADC12CTL0 |= ADC12SC; // Start conversion while (!(ADC12IFG & BIT0)); __no_operation(); // SET BREAKPOINT HERE } }
cc430x613x_adc12_06.c ADC12, Repeated Sequence of Conversions
//****************************************************************************** // CC430F613x Demo - ADC12_A, Repeated Sequence of Conversions // // Description: This example shows how to perform a repeated sequence of // conversions using "repeat sequence-of-channels" mode. AVcc is used for the // reference and repeated sequence of conversions is performed on Channels A0, // A1, A2, and A3. Each conversion result is stored in ADC12MEM0, ADC12MEM1, // ADC12MEM2, and ADC12MEM3 respectively. After each sequence, the 4 conversion // results are moved to A0results[], A1results[], A2results[], and A3results[]. // Test by applying voltages to channels A0 - A3. Open a watch window in // debugger and view the results. Set Breakpoint1 in the index increment line // to see the array values change sequentially and Breakpoint2 to see the entire // array of conversion results in A0results[], A1results[], A2results[], and // A3results[]for the specified Num_of_Results. // // Note that a sequence has no restrictions on which channels are converted. // For example, a valid sequence could be A0, A3, A2, A4, A2, A1, A0, and A7. // See the CC430 User's Guide for instructions on using the ADC12_A. // // CC430F6137 // ----------------- // /|\| | // | | | // --|RST | // | | // Vin0 -->|P2.0/A0 | // Vin1 -->|P2.1/A1 | // Vin2 -->|P2.2/A2 | // Vin3 -->|P2.3/A3 | // | | // // M. Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" #define Num_of_Results 8 volatile unsigned int A0results[Num_of_Results]; volatile unsigned int A1results[Num_of_Results]; volatile unsigned int A2results[Num_of_Results]; volatile unsigned int A3results[Num_of_Results]; void main(void) { WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer P2SEL = 0x0F; // Enable A/D channel inputs ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT0_8; // Turn on ADC12_A, extend sampling time // to avoid overflow of results ADC12CTL1 = ADC12SHP+ADC12CONSEQ_3; // Use sampling timer, repeated sequence ADC12MCTL0 = ADC12INCH_0; // ref+=AVcc, channel = A0 ADC12MCTL1 = ADC12INCH_1; // ref+=AVcc, channel = A1 ADC12MCTL2 = ADC12INCH_2; // ref+=AVcc, channel = A2 ADC12MCTL3 = ADC12INCH_3+ADC12EOS; // ref+=AVcc, channel = A3, end seq. ADC12IE = 0x08; // Enable ADC12IFG.3 ADC12CTL0 |= ADC12ENC; // Enable conversions ADC12CTL0 |= ADC12SC; // Start conversion - software trigger __bis_SR_register(LPM0_bits + GIE); // Enter LPM0, Enable interrupts __no_operation(); // For debugger } #pragma vector=ADC12_VECTOR __interrupt void ADC12ISR (void) { static unsigned int index = 0; switch(__even_in_range(ADC12IV,34)) { case 0: break; // Vector 0: No interrupt case 2: break; // Vector 2: ADC overflow case 4: break; // Vector 4: ADC timing overflow case 6: break; // Vector 6: ADC12IFG0 case 8: break; // Vector 8: ADC12IFG1 case 10: break; // Vector 10: ADC12IFG2 case 12: // Vector 12: ADC12IFG3 A0results[index] = ADC12MEM0; // Move A0 results, IFG is cleared A1results[index] = ADC12MEM1; // Move A1 results, IFG is cleared A2results[index] = ADC12MEM2; // Move A2 results, IFG is cleared A3results[index] = ADC12MEM3; // Move A3 results, IFG is cleared index++; // Increment results index, modulo; Set Breakpoint1 here if (index == 8) index = 0; // Reset index, Set breakpoint 2 here case 14: break; // Vector 14: ADC12IFG4 case 16: break; // Vector 16: ADC12IFG5 case 18: break; // Vector 18: ADC12IFG6 case 20: break; // Vector 20: ADC12IFG7 case 22: break; // Vector 22: ADC12IFG8 case 24: break; // Vector 24: ADC12IFG9 case 26: break; // Vector 26: ADC12IFG10 case 28: break; // Vector 28: ADC12IFG11 case 30: break; // Vector 30: ADC12IFG12 case 32: break; // Vector 32: ADC12IFG13 case 34: break; // Vector 34: ADC12IFG14 default: break; } }
cc430x613x_adc12_07.c ADC12, Repeated Single Channel Conversions
//****************************************************************************** // CC430F613x Demo - ADC12_A, Repeated Single Channel Conversions // // Description: This example shows how to perform repeated conversions on a // single channel using "repeat-single-channel" mode. AVcc is used for the // reference and repeated conversions are performed on Channel A0. Each // conversion result is moved to an 8-element array called results[]. Test by // applying a voltage to channel A0, then running. Open a watch window in // debugger and view the results. Set Breakpoint1 in the index increment line // to see the array value change sequentially and Breakpoint to see the entire // array of conversion results in "results[]" for the specified Num_of_Results. // This can run even in LPM4 mode as ADC has its own clock (MODOSC) // // CC430F6137 // ----------------- // /|\| | // | | | // --|RST | // | | // Vin -->|P2.0/A0 | // | | // // // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" #define Num_of_Results 8 volatile unsigned int results[Num_of_Results]; // Needs to be global in this // example. Otherwise, the // compiler removes it because it // is not used for anything. void main(void) { WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer P2SEL |= 0x01; // Enable A/D channel A0 /* Initialize ADC12_A */ ADC12CTL0 = ADC12ON+ADC12SHT0_8+ADC12MSC; // Turn on ADC12, set sampling time // set multiple sample conversion ADC12CTL1 = ADC12SHP+ADC12CONSEQ_2; // Use sampling timer, set mode ADC12IE = 0x01; // Enable ADC12IFG.0 ADC12CTL0 |= ADC12ENC; // Enable conversions ADC12CTL0 |= ADC12SC; // Start conversion __bis_SR_register(LPM4_bits + GIE); // Enter LPM4, Enable interrupts __no_operation(); // For debugger } #pragma vector=ADC12_VECTOR __interrupt void ADC12ISR (void) { static unsigned char index = 0; switch(__even_in_range(ADC12IV,34)) { case 0: break; // Vector 0: No interrupt case 2: break; // Vector 2: ADC overflow case 4: break; // Vector 4: ADC timing overflow case 6: // Vector 6: ADC12IFG0 results[index] = ADC12MEM0; // Move results index++; // Increment results index, modulo; Set Breakpoint1 here if (index == 8) index = 0; // Reset the index; Set Breakpoint here case 8: break; // Vector 8: ADC12IFG1 case 10: break; // Vector 10: ADC12IFG2 case 12: break; // Vector 12: ADC12IFG3 case 14: break; // Vector 14: ADC12IFG4 case 16: break; // Vector 16: ADC12IFG5 case 18: break; // Vector 18: ADC12IFG6 case 20: break; // Vector 20: ADC12IFG7 case 22: break; // Vector 22: ADC12IFG8 case 24: break; // Vector 24: ADC12IFG9 case 26: break; // Vector 26: ADC12IFG10 case 28: break; // Vector 28: ADC12IFG11 case 30: break; // Vector 30: ADC12IFG12 case 32: break; // Vector 32: ADC12IFG13 case 34: break; // Vector 34: ADC12IFG14 default: break; } }
cc430x613x_adc12_09.c ADC12, Sequence of Conversions (non-repeated)
//****************************************************************************** // CC430F6137 Demo - ADC12_A, Sequence of Conversions (non-repeated) // // Description: This example shows how to perform A/D conversions on a sequence // of channels. A single sequence of conversions is performed - one conversion // each on channels A0, A1, A2, and A3. Each conversion uses AVcc and AVss for // the references. The conversion results are stored in ADC12MEM0, ADC12MEM1, // ADC12MEM2, and ADC12MEM3 respectively and are moved to 'results[]' upon // completion of the sequence. Test by applying voltages to pins A0, A1, A2, // and A3, then setting and running to a break point at the "_BIC..." // instruction in the ISR. To view the conversion results, open a watch window // in debugger and view 'results' or view ADC12MEM0, ADC12MEM1, ADC12MEM2, and // ADC12MEM3 in an ADC12 SFR window. // This can run even in LPM4 mode as ADC has its own clock // Note that a sequence has no restrictions on which channels are converted. // For example, a valid sequence could be A0, A3, A2, A4, A2, A1, A0, and A7. // See the CC430 User's Guide for instructions on using the ADC12. // // CC430F6137 // ----------------- // /|\| | // | | | // --|RST | // | | // Vin0 -->|P2.0/A0 | // Vin1 -->|P2.1/A1 | // Vin2 -->|P2.2/A2 | // Vin3 -->|P2.3/A3 | // | | // // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" volatile unsigned int results[4]; // Needs to be global in this example // Otherwise, the compiler removes it // because it is not used for anything. void main(void) { WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer P2SEL = 0x0F; // Enable A/D channel inputs /* Initialize ADC12_A */ ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT0_2; // Turn on ADC12, set sampling time ADC12CTL1 = ADC12SHP+ADC12CONSEQ_1; // Use sampling timer, single sequence ADC12MCTL0 = ADC12INCH_0; // ref+=AVcc, channel = A0 ADC12MCTL1 = ADC12INCH_1; // ref+=AVcc, channel = A1 ADC12MCTL2 = ADC12INCH_2; // ref+=AVcc, channel = A2 ADC12MCTL3 = ADC12INCH_3+ADC12EOS; // ref+=AVcc, channel = A3, end seq. ADC12IE = 0x08; // Enable ADC12IFG.3 ADC12CTL0 |= ADC12ENC; // Enable conversions while(1) { ADC12CTL0 |= ADC12SC; // Start convn - software trigger __bis_SR_register(LPM4_bits + GIE); // Enter LPM4, Enable interrupts __no_operation(); // For debugger } } #pragma vector=ADC12_VECTOR __interrupt void ADC12ISR (void) { switch(__even_in_range(ADC12IV,34)) { case 0: break; // Vector 0: No interrupt case 2: break; // Vector 2: ADC overflow case 4: break; // Vector 4: ADC timing overflow case 6: break; // Vector 6: ADC12IFG0 case 8: break; // Vector 8: ADC12IFG1 case 10: break; // Vector 10: ADC12IFG2 case 12: // Vector 12: ADC12IFG3 results[0] = ADC12MEM0; // Move results, IFG is cleared results[1] = ADC12MEM1; // Move results, IFG is cleared results[2] = ADC12MEM2; // Move results, IFG is cleared results[3] = ADC12MEM3; // Move results, IFG is cleared __bic_SR_register_on_exit(LPM4_bits); // Exit active CPU, SET BREAKPOINT HERE case 14: break; // Vector 14: ADC12IFG4 case 16: break; // Vector 16: ADC12IFG5 case 18: break; // Vector 18: ADC12IFG6 case 20: break; // Vector 20: ADC12IFG7 case 22: break; // Vector 22: ADC12IFG8 case 24: break; // Vector 24: ADC12IFG9 case 26: break; // Vector 26: ADC12IFG10 case 28: break; // Vector 28: ADC12IFG11 case 30: break; // Vector 30: ADC12IFG12 case 32: break; // Vector 32: ADC12IFG13 case 34: break; // Vector 34: ADC12IFG14 default: break; } }
cc430x613x_adc12_10.c ADC12, Sample A10 Temp and Convert to oC and oF
//****************************************************************************** // CC430F613x Demo - ADC12_A, Sample A10 Temp and Convert to oC and oF // // Description: A single sample is made on A10 with reference to internal // 1.5V Vref. Software sets ADC12SC to start sample and conversion - ADC12SC // automatically cleared at EOC. ADC12 internal oscillator times sample // and conversion. In Mainloop MSP430 waits in LPM4 to save power until // ADC10 conversion complete, ADC12_ISR will force exit from any LPMx in // Mainloop on reti. // ACLK = n/a, MCLK = SMCLK = default DCO ~ 1.045MHz, ADC12CLK = ADC12OSC // // Uncalibrated temperature measured from device to devive will vary due to // slope and offset variance from device to device - please see datasheet. // // CC430F6137 // ----------------- // /|\| XIN|- // | | | // --|RST XOUT|- // | | // |A10 | // // M. Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" volatile long temp; volatile long IntDegF; volatile long IntDegC; void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT /* Initialize the shared reference module */ REFCTL0 |= REFMSTR + REFVSEL_0 + REFON; // Enable internal 1.5V reference /* Initialize ADC12_A */ ADC12CTL0 = ADC12SHT0_8 + ADC12ON; // Set sample time ADC12CTL1 = ADC12SHP; // Enable sample timer ADC12MCTL0 = ADC12SREF_1 + ADC12INCH_10; // ADC input ch A10 => temp sense ADC12IE = 0x001; // ADC_IFG upon conv result-ADCMEMO __delay_cycles(75); // 35us delay to allow Ref to settle // based on default DCO frequency. // See Datasheet for typical settle // time. ADC12CTL0 |= ADC12ENC; while(1) { ADC12CTL0 |= ADC12SC; // Sampling and conversion start __bis_SR_register(LPM4_bits + GIE); // LPM4 with interrupts enabled __no_operation(); // Temperature in Celsius // ((A10/4096*1500mV) - 894mV)*(1/3.66mV) = (A10/4096*410) - 244 // = (A10 - 2438) * (410 / 4096) IntDegC = ((temp - 2438) * 410) / 4096; // Temperature in Fahrenheit // ((A10/4096*1500mV) - 829mV)*(1/2.033mV) = (A10/4096*738) - 408 // = (A10 - 2264) * (738 / 4096) IntDegF = ((temp - 2264) * 738) / 4096; __no_operation(); // SET BREAKPOINT HERE } } #pragma vector=ADC12_VECTOR __interrupt void ADC12ISR (void) { switch(__even_in_range(ADC12IV,34)) { case 0: break; // Vector 0: No interrupt case 2: break; // Vector 2: ADC overflow case 4: break; // Vector 4: ADC timing overflow case 6: // Vector 6: ADC12IFG0 temp = ADC12MEM0; // Move results, IFG is cleared __bic_SR_register_on_exit(LPM4_bits); // Exit active CPU break; case 8: break; // Vector 8: ADC12IFG1 case 10: break; // Vector 10: ADC12IFG2 case 12: break; // Vector 12: ADC12IFG3 case 14: break; // Vector 14: ADC12IFG4 case 16: break; // Vector 16: ADC12IFG5 case 18: break; // Vector 18: ADC12IFG6 case 20: break; // Vector 20: ADC12IFG7 case 22: break; // Vector 22: ADC12IFG8 case 24: break; // Vector 24: ADC12IFG9 case 26: break; // Vector 26: ADC12IFG10 case 28: break; // Vector 28: ADC12IFG11 case 30: break; // Vector 30: ADC12IFG12 case 32: break; // Vector 32: ADC12IFG13 case 34: break; // Vector 34: ADC12IFG14 default: break; } }
COMP_B;
cc430x613x_compB_01.c COMPB output Toggle in LPM4; internal 2.0V reference
//****************************************************************************** // CC430x613x Demo - COMPB output Toggle in LPM4; internal 2.0V reference // // Description: Use CompB and internal reference to determine if input'Vcompare' // is high of low. When Vcompare exceeds 2.0V CBOUT goes high and when // Vcompare is less than 2.0V then CBOUT goes low. // Connect P1.6/CBOUT to P1.0 externally to see the LED toggle accordingly. // // CC430x613x // ------------------ // /|\| | // | | | // --|RST P2.0/CB0|<--Vcompare // | | // | P1.6/CBOUT|----> 'high'(Vcompare>2.0V); 'low'(Vcompare<2.0V) // | | | // | P1.0 |__| LED 'ON'(Vcompare>2.0V); 'OFF'(Vcompare<2.0V) // | | // // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= BIT6; // P1.6 output direction P1SEL |= BIT6; // Select CBOUT function on P1.6/CBOUT PMAPPWD = 0x02D52; // Get write-access to port mapping regs P1MAP6 = PM_CBOUT0; // Map CBOUT output to P1.6 PMAPPWD = 0; // Lock port mapping registers P2SEL |= BIT0; // Select CB0 input for P2.0 // Setup ComparatorB CBCTL0 |= CBIPEN + CBIPSEL_0; // Enable V+, input channel CB0 CBCTL1 |= CBPWRMD_1; // normal power mode CBCTL2 |= CBRSEL; // VREF is applied to -terminal CBCTL2 |= CBRS_3+CBREFL_2; // R-ladder off; bandgap ref voltage (1.2V) // supplied ref amplifier to get Vcref=2.0V (CBREFL_2) CBCTL3 |= BIT0; // Input Buffer Disable @P6.0/CB0 CBCTL1 |= CBON; // Turn On ComparatorB __delay_cycles(75); __bis_SR_register(LPM4_bits); // Enter LPM4 __no_operation(); // For debug }
cc430x613x_compB_03.c COMPB interrupts; internal 1.5V reference
//****************************************************************************** // CC430x613x Demo - COMPB interrupts; internal 1.5V reference // // Description: Use CompB and internal reference to determine if input'Vcompare' // is high of low. For the first time, when Vcompare exceeds the 1.5V internal // reference, CBIFG is set and device enters the CompB ISR. In the ISR CBIES is // toggled such that when Vcompare is less than 1.5V internal reference, CBIFG is set. // LED is toggled inside the CompB ISR // // CC430x613x // ------------------ // /|\| | // | | | // --|RST P2.0/CB0 |<--Vcompare // | | // | P1.0 |--> LED 'ON'(Vcompare<1.5V); 'OFF'(Vcompare>1.5V) // | | // // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= BIT0; // P1.0/LED output direction P2SEL |= BIT0; /* Setup ComparatorB */ CBCTL0 |= CBIPEN + CBIPSEL_0; // Enable V+, input channel CB0 CBCTL1 |= CBPWRMD_1; // normal power mode CBCTL2 |= CBRSEL; // VREF is applied to -terminal CBCTL2 |= CBRS_3+CBREFL_1; // R-ladder off; bandgap ref voltage (1.2V) // amplify to get Vcref=1.5V (CBREFL_2) CBCTL3 |= BIT0; // Input Buffer Disable @P2.0/CB0 CBCTL1 |= CBON; // Turn On ComparatorB __delay_cycles(75); // Delay for shared ref to stabilize CBINT &= ~(CBIFG + CBIIFG); // Clear any errant interrupts CBINT |= CBIE; // Enable CompB Interrupt on rising // edge of CBIFG (CBIES=0) __bis_SR_register(LPM4_bits+GIE); // Enter LPM4 with inetrrupts enabled __no_operation(); // For debug } // Comp_B ISR - LED Toggle #pragma vector=COMP_B_VECTOR __interrupt void Comp_B_ISR (void) { CBCTL1 ^= CBIES; // Toggles interrupt edge CBINT &= ~CBIFG; // Clear Interrupt flag P1OUT ^= 0x01; // Toggle P1.0 }
cc430x613x_compB_04.c CBOUT from LPM4; CompB in ultra low power mode; Vref = Vcc*1/2
//****************************************************************************** // CC430x613x Demo - CBOUT from LPM4; CompB in ultra low power mode; Vref = Vcc*1/2 // // Description: Use CompB and shared reference to determine if input 'Vcompare' // is high of low. When Vcompare exceeds Vcc*1/2 CBOUT goes high and when // Vcompare is less than Vcc*1/2 then CBOUT goes low. // Connect P1.6/CBOUT to P1.0 externally to see the LED toggle accordingly. // // CC430x613x // ------------------ // /|\| | // | | | // --|RST P2.0/CB0 |<--Vcompare // | | // | P1.6/CBOUT|----> 'high'(Vcompare>Vcc*1/2); 'low'(Vcompare<Vcc*1/2) // | | | // | P1.0 |__| LED 'ON'(Vcompare>Vcc*1/2); 'OFF'(Vcompare<Vcc*1/2) // | | // // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= BIT6; // P1.6 output direction P1SEL |= BIT6; // Select CBOUT function on P1.6/CBOUT PMAPPWD = 0x02D52; // Get write-access to port mapping regs P1MAP6 = PM_CBOUT0; // Map CBOUT output to P1.6 PMAPPWD = 0; // Lock port mapping registers P2SEL |= BIT0; // Select CB0 input for P2.0 /* Setup ComparatorB */ CBCTL0 |= CBIPEN+CBIPSEL_0; // Enable V+, input channel CB0 CBCTL1 |= CBMRVS; // CMRVL selects the refV - VREF0 CBCTL1 |= CBPWRMD_2; // Ultra-Low Power mode CBCTL2 |= CBRSEL; // VREF is applied to -terminal CBCTL2 |= CBRS_1+CBREF04; // VCC applied to R-ladder; VREF0 is Vcc*1/2 CBCTL3 |= BIT0; // Input Buffer Disable @P2.0/CB0 CBCTL1 |= CBON; // Turn On ComparatorB __delay_cycles(75); __bis_SR_register(LPM4_bits); // Enter LPM4 __no_operation(); // For debug }
cc430x613x_compB_05.c COMPB Hysteresis, CBOUT Toggle in LPM4; High speed mode
//****************************************************************************** // CC430x613x Demo - COMPB Hysteresis, CBOUT Toggle in LPM4; High speed mode // // Description: Use CompB and shared reference to determine if input 'Vcompare' // is high of low. Shared reference is configured to generate hysteresis. // When Vcompare exceeds Vcc*3/4 CBOUT goes high and when Vcompare is less // than Vcc*1/4 then CBOUT goes low. // Connect P1.6/CBOUT to P1.0 externally to see the LED toggle accordingly. // // CC430x613x // ------------------ // /|\| | // | | | // --|RST P2.0/CB0 |<--Vcompare // | | // | P1.6/CBOUT|----> 'high'(Vcompare>Vcc*3/4); 'low'(Vcompare<Vcc*1/4) // | | | // | P1.0 |__| LED 'ON'(Vcompare>Vcc*3/4); 'OFF'(Vcompare<Vcc*1/4) // | | // // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= BIT6; // P1.6 output direction P1SEL |= BIT6; // Select CBOUT function on P1.6/CBOUT PMAPPWD = 0x02D52; // Get write-access to port mapping regs P1MAP6 = PM_CBOUT0; // Map CBOUT output to P1.6 PMAPPWD = 0; // Lock port mapping registers P2SEL |= BIT0; // Select CB0 input for P2.0 // Setup ComparatorB CBCTL0 |= CBIPEN + CBIPSEL_0; // Enable V+, input channel CB0 CBCTL1 |= CBPWRMD_0; // CBMRVS=0 => select VREF1 as ref when CBOUT // is high and VREF0 when CBOUT is low // High-Speed Power mode CBCTL2 |= CBRSEL; // VRef is applied to -terminal CBCTL2 |= CBRS_1+CBREF13; // VREF1 is Vcc*1/4 CBCTL2 |= CBREF04+CBREF03; // VREF0 is Vcc*3/4 CBCTL3 |= BIT0; // Input Buffer Disable @P6.0/CB0 CBCTL1 |= CBON; // Turn On ComparatorB __bis_SR_register(LPM4_bits); // Enter LPM4 __no_operation(); // For debug }
cc430x613x_compB_06.c COMPB and TIMERAx interaction (TA0.1, TA1.1)
//****************************************************************************** // CC430x613x Demo - COMPB and TIMERAx interaction (TA0.1, TA1.1) // // Description: Use CompB to determine if input, Vcompare has a duty cycle // greater than 50%. When Vcompare exceeds Vcc*3/4 then TimerA0 captures the // time (TA0CCR1). When Vcompare is less than Vcc*1/4 then TimerA1 captures the // time (TA1CCR1) and resets the timers for TIMERA0 and TIMERA1. If TA0CCR1 is // greater than TA1CCR1/2, then turn on the LED. If TA0CCR1 is less than // TA1CCR1/2, then turn off the LED. // // Clocks: ACLK = REFO; MCLK = SMCLK = 12MHz // // CC430x613x // ------------------ // /|\| | // | | | // --|RST CB0 |<--Vcompare (200Hz<f<1Mhz) (vary dutycycle) // | | // | | // | P1.0|-->LED ('ON' if dutycycle > 50%; 'OFF' if dutycycle < 50%) // // M Morales // Texas Instruments Inc. // April 2009 // Built with CCE Version: 3.2.2 and IAR Embedded Workbench Version: 4.11B //****************************************************************************** #include "cc430x613x.h" void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT // Setup UCS: ACLK = REFO; MCLK = SMCLK = 12MHz UCSCTL4 = SELA__REFOCLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV; UCSCTL3 |= SELREF__REFOCLK; // Set DCO FLL reference = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz // (N + 1) * FLLRef = Fdco // (374 + 1) * 32768 = 12MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle __delay_cycles(375000); // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag P2SEL |= BIT0; // Enable CB0 input // Setup ComparatorB CBCTL0 |= CBIPEN + CBIPSEL_0; // Enable V+, input channel CB0 CBCTL1 |= CBPWRMD_0; // CBMRVS=0 => select VREF1 as ref when CBOUT // is high and VREF0 when CBOUT is low // High-Speed Power mode CBCTL2 |= CBRSEL; // Ref is applied to -terminal CBCTL2 |= CBRS_1+CBREF13; // VREF1 is Vcc*1/4 CBCTL2 |= CBREF04+CBREF03; // VREF0 is Vcc*3/4 CBCTL3 |= BIT0; // Input Buffer Disable @P6.0/CB0 CBCTL1 |= CBON; // Turn On ComparatorB // Setup Timer_A0 and Timer_A1 // Internally CBOUT --> TA0CCTL1:CCIB (TA0.1) // +-> TA1CCTL1:CCIB (TA1.1) TA0CTL = TASSEL_2 + MC_1; // SMCLK, upmode TA1CTL = TASSEL_2 + MC_1; // SMCLK, upmode TA0CCR0 = 0xFFFF; TA1CCR0 = 0xFFFF; TA0CCTL1 = CM_2+SCS+CAP+CCIS_1; // Capture Falling Edge TA1CCTL1 = CM_1+SCS+CAP+CCIS_1+CCIE; // Capture Rising Edge, Enable Interrupt P1DIR |= BIT0; // Set P1.0/LED to output __bis_SR_register(LPM3_bits+GIE); // Enter LPM0 with global interrupts enabled __no_operation(); // For Debug } #pragma vector=TIMER1_A1_VECTOR __interrupt void Timer_A(void) { unsigned int temp; switch( TA1IV ) { case 2: TA0CCR0 = 0; TA1CCR0 = 0; TA0CCR0 = 0xFFFF; TA1CCR0 = 0xFFFF; // Halt and resart TimerA0 and A1 counters temp = TA1CCR1>>1; // Compare On and off time of input signal if(TA0CCR1 > temp) P1OUT |= BIT0; else P1OUT &= ~BIT0; break; case 4: break; // CCR2 not used case 6: break; // CCR3 not used case 8: break; // CCR4 not used case 10: break; // CCR5 not used case 12: break; // Reserved not used case 14: // Overflow __no_operation(); while(1); // If input frequency < 200Hz, trap here default: break; } }