AARCH64内核highlights

39bits地址线，4K页时3级页表，64K页时2级页表。

In terms of MMU, it currently supports 39-bit address space for user and kernel (each) with 3-level page table and 4KB pages or 2-level page table and 64KB pages (see Documentation/aarch64/memory.txt). The virtual address space can be extended to 48-bit. 

32bits兼容模式，但只允许在4k页的模式下。

二者无法同时工作，因为转换需要exception来完成。

Compat (32-bit) user applications (ARM EABI only) are supported with the 4KB page configuration. There is no interworking between AArch32 and AArch64 code (the architecture requires an exception entry/exit to change the mode). 

linaro的文档

http://people.linaro.org/~rikuvoipio/aarch64-talk/#/

userspace的ABI文档

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.swdev.abi/index.html

其它知识：

http://community.arm.com/groups/processors/blog/2011/03/22/memory-access-ordering--an-introduction