hdmi转 bt1120方案.

        我们先看下下面的架构图,HDMI 4k@30hz,想进3536没有找到相应的芯片转为 bt1120.FPGA就充当了转化作用。 Xilinx最近出了一个Hdmi_ipcore.就想把他用起来。所以就有下面的架构图。我要做的工作其中之一就是要把 标准的VESA信号转为 BT1120出去.

现在我要做的就是把TTL（YCbCr 4:2:2）转为 BT1120给海思3531。我把思路说一下：

如上图所示，当收到第一个nvsync下降沿，然后 de 上升沿的时候，开始计数。这样就可以在相应的位置上填上相应的标志位和有效像素。当然需要用到状态机。

最后我附上，之前写的testbench关于1920 x 1080 @ 60hz.VESA标准。

`timescale  1 ps/1ps  
module tb;  



parameter H_D0 = 88;
parameter H_D1 = 44;
parameter H_D2 = 148;
parameter H_D = 1920;

parameter V_D0= 4;
parameter V_D1 = 5;
parameter V_D2 = 36;
parameter V_D = 1080;




reg                   clock_source;
reg                   clk_rd;
reg                   reset_n;
reg                   de_rd;
reg                   nhsync_rd;
reg                   nvsync_rd;
reg   [11:0]          hcounter_rd;
reg   [11:0]          vcounter_rd;
reg   [15:0]          data_input_a;
wire                de_rd_dly;
wire                nhsync_rd_dly;
wire                nvsync_rd_dly;
wire   [15:0]       data_input_a_dly;
wire   [15: 0]      bt_data_o;


always #3367  clk_rd = ~clk_rd;

initial 
  begin
    clk_rd = 0;
  	 clock_source =  0;
    reset_n = 0;
    #200000;
    reset_n = 1;
  end
 
//GSR GSR_INST (.GSR(1'b1));  
//PUR PUR_INST (.PUR(1'b1)); 


always @(posedge clk_rd or negedge reset_n)
begin
  if (~reset_n)
    hcounter_rd <= 12'b0;
  else if (hcounter_rd == (H_D + H_D0 + H_D1 + H_D2 - 1)) 
    hcounter_rd <= 12'b0;
  else
    hcounter_rd <= hcounter_rd + 12'h1;
end

always @(posedge clk_rd or negedge reset_n)
begin
  if (~reset_n)
    vcounter_rd <= 12'h0;
  else if ((vcounter_rd == (V_D + V_D0 + V_D1 + V_D2 - 1))  && (hcounter_rd == (H_D + H_D0 + H_D1 + H_D2 - 1)))
    vcounter_rd <= 12'h0;
  else if (hcounter_rd == (H_D + H_D0 + H_D1 + H_D2 - 1))  ////
    vcounter_rd <= vcounter_rd + 12'h1;
end

always @(posedge clk_rd)
begin
 if (((vcounter_rd >= V_D1 + V_D2 + V_D0) && (vcounter_rd < (V_D + V_D1 + V_D2 + V_D0))) && (hcounter_rd >= H_D0 + H_D1 + H_D2 -1) && (hcounter_rd < H_D0 + H_D1 + H_D2 + H_D - 1)) // 280 
    de_rd <= 1'b1;
  else
    de_rd <= 1'b0;
end



always @(posedge clk_rd or negedge reset_n)
begin
  if (~reset_n)
    data_input_a <= 16'h0;   // 1121    41
  else if (((vcounter_rd >= V_D1 + V_D2 + V_D0) && (vcounter_rd < (V_D + V_D1 + V_D2 + V_D0))) && (hcounter_rd >= H_D0 + H_D1 + H_D2 -1) && (hcounter_rd < H_D0 + H_D1 + H_D2 + H_D - 1)) // 280 
    data_input_a <=  data_input_a + 16'h2;    
end





always @(posedge clk_rd)
begin
 if ((hcounter_rd >= H_D0 -1) && (hcounter_rd < H_D0 + H_D1 - 1))
    nhsync_rd <= 1'b1;
  else
    nhsync_rd <= 1'b0;
end

always @(posedge clk_rd)
begin
if (((vcounter_rd < V_D0 + V_D1) && (vcounter_rd > V_D0)) || ((vcounter_rd == V_D0) && (hcounter_rd >= H_D0 -1)) || ((vcounter_rd == V_D0 + V_D1) && (hcounter_rd < H_D0 -1)))
    nvsync_rd <= 1'b1;
  else
    nvsync_rd <= 1'b0;
end

/*
bt_rx U_BT(
	      .reset_n(reset_n),
		  .clk(clk_rd),
	      .de_i(de_rd),
          .nhsync_i(nhsync_rd),
          .nvsync_i(nvsync_rd),
          .ycbcr_i(data_input_a),
		  .bt_data_o(bt_data_o)
				);
*/
endmodule