OpenRisc-2-C to Verilog

引言

如何将C语言代码转换成verilog HDL或者VHDL呢？
 

2.1 在线转换：

http://c-to-verilog.com/online.html

C-to-Verilog.com是海法（Haifa）大学高层次综合领域的一个学术研究而产生的一个网站。
这个网站所用的编译器是SystemRacer综合系统的一个修改版本。这个编译器的源码可用于研究目的，并且已经发给了很多编译器的研究组织。
此外还有一些文章可供参考，这些文章介绍了这个综合器的实现原理。

 

2.2 下载源码，然后安装，再使用。

 

源码，我已经上传，GPL3许可；还有介绍这个综合器实现原理的文章，文章我也已经上传（这些文章都是发表在顶级期刊或会议的优秀paper，需要付费才能下载的），和源码放在一起：

http://download.csdn.net/detail/rill_zhen/4797683

 

2.3 注意

需要LLVM 2.5的支持。LLVM是构架编译器(compiler)的框架系统，
以C++编写而成，用于优化以任意程序语言编写的程序的编译时间(compile-time)、链接时间(link-time)、运行时间(run-time)以及空闲时间(idle-time)，
对开发者保持开放，并兼容已有脚本。
LLVM计划启动于2000年，最初由University of Illinois at Urbana-Champaign的Chris Lattner主持开展。
2006年Chris Lattner加盟Apple Inc.并致力于LLVM在Apple开发体系中的应用。
Apple也是LLVM计划的主要资助者。

 

2.4 测试：

先贴一个截屏吧：

 

C代码：

void rill_main(void) 
{ 
int i = 0;
int j = 0;

    for (int i=0; i<2; i++) 
        j = i; 
}

点击“综合”，生成verilogHDL代码：包含模块代码和testbench代码，呵呵，连测试代码都自动生成了，想的真周到。

verilog 模块代码：

/*       This module was generated by c-to-verilog.com
 * THIS SOFTWARE IS PROVIDED BY www.c-to-verilog.com ''AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL c-to-verilog.com BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES)
 * 
 * Found a bug? email [email protected] 
 */


module rill_main  (clk, reset, rdy,// control 
	return_value); // params 
 input wire clk;
 input wire reset;
 output rdy;
 reg rdy;
 output return_value;
 reg return_value;



 // Number of states:1
 reg [0:0] eip;
 parameter entry0 = 1'd0;

// Assign part (0)


always @(posedge clk)
 begin
  if (reset)
   begin
    $display("@hard reset");
    eip<=0;
    rdy<=0;
   end


// Datapath 


// Control 
case (eip)
entry0:
begin
	 rdy <= 1;
 return_value <= 0;
 $finish();
end
 endcase //eip
end //always @(..)

endmodule



// -- Library components --  

module mul (clk, a, b, p);
output reg [31:0] p;
input [31:0] a;
input [31:0] b;
input clk;reg [31:0] t0;
reg [31:0] t1;
reg [31:0] t2;
reg [31:0] t3;
always @(posedge clk)begin
t0 <= a * b;
t1 <= t0;
t2 <= t1;
t3 <= t2;
p <=t3;
end
endmodule


module div (clk, a, b, p);
output reg [31:0] p;
input [31:0] a;
input [31:0] b;
input clk;reg [31:0] t0;
reg [31:0] t1;
reg [31:0] t2;
reg [31:0] t3;
always @(posedge clk)begin
t0 <= a / b;
t1 <= t0;
t2 <= t1;
t3 <= t2;
p <=t3;
end
endmodule


module shl (clk, a, b, p);
output reg [31:0] p;
input [31:0] a;
input [31:0] b;
input clk;reg [31:0] t0;
reg [31:0] t1;
reg [31:0] t2;
reg [31:0] t3;
always @(posedge clk)begin
t0 <= a << b;
t1 <= t0;
t2 <= t1;
t3 <= t2;
p <=t3;
end
endmodule

// Dual port memory block
module xram (out0, din0, addr0, we0, clk0,
           out1, din1, addr1, we1, clk1);
  parameter ADDRESS_WIDTH = 16;
  parameter WORD_WIDTH = 32;
  output [WORD_WIDTH-1:0] out0;
  input [WORD_WIDTH-1:0] din0;
  input [ADDRESS_WIDTH-1:0] addr0;
  input we0;
  input clk0;
  output [WORD_WIDTH-1:0] out1;
  input [WORD_WIDTH-1:0] din1;
  input [ADDRESS_WIDTH-1:0] addr1;
  input we1;
  input clk1;
  reg [WORD_WIDTH-1:0] mem[1<<ADDRESS_WIDTH-1:0];
   integer i;
   initial begin
       for (i = 0; i < (1<<(ADDRESS_WIDTH-1)); i = i + 1) begin
       mem[i] <= i;
     end
   end
  assign out0 = mem[addr0];
  assign out1 = mem[addr1];
  always @(posedge clk0)begin
      if (we0) begin
          mem[addr0] = din0;
          $display($time,"w mem[%d] == %d; in=%d",addr0, mem[addr0],din0);
      end
  end
  always @(posedge clk1)begin
      if (we1) begin
          mem[addr1] = din1;
          $display($time,"w mem[%d] == %d; in=%d",addr0, mem[addr0],din0);
      end 
  end
endmodule

 

此外还会生成testbench代码（和上面的代码在同一个文件中）：

 // Test Bench 


module rill_main_test;
 wire rdy;
 reg reset, clk;
 always #5 clk = ~clk;
 wire return_value;
rill_main instance1 (clk, reset, rdy,// control 
	return_value); // params 
initial begin
 clk = 0;
 $monitor("return = %b, 0x%x", rdy,  return_value);

 // Configure the values below to test the module
 #5 reset = 1; #5 reset = 0;
end

endmodule //main_test

 

2.5 C to VHDL

此外还可以将C代码转换成VHDL，请参考：

http://tce.cs.tut.fi/

简介：

TCE is a toolset for designing application-specific processors (ASP) based on    the Transport triggered architecture (TTA). The toolset provides a complete    co-design flow from C programs down to synthesizable VHDL and parallel program    binaries. Processor customization points include the register files, function    units, supported operations, and the interconnection network.

    TCE has been developed internally in the Tampere University of Technology    since the early 2003. The current source code base consists of roughly 400 000    lines of C++ code.