u-boot1.1.6移植之Diff比较
46 fun_diff()
47 {
48 #board/san2440/lowlevel_init.S
49 #board/san2440/san2440.c
50 #include/configs/san2440.h
51 #cpu/arm920t/start.S
52
53 #include/s3c24x0.h
54 #cpu/arm920t/s3c24x0/interrupts.c
55 #cpu/arm920t/s3c24x0/serial.c
56 #cpu/arm920t/s3c24x0/speed.c
57 #cpu/arm920t/s3c24x0/usb_ohci.c
58 #cpu/arm920t/s3c24x0/usb.c
59 #cpu/arm920t/s3c24x0/i2c.c
60 #drivers/usb/usb_ohci.c
61 #drivers/rtc/s3c24x0_rtc.c
62 #lib_arm/board.c
63 old="sanEmbeded/u-boot-1.1.6"
64 new="EmbedSky/u-boot-1.1.6"
65 config_file="patch/patch-uboot.config" diff配置文件，详细参考附件
66
67 patch_file=(`sed 's/^.*////g' "$config_file"`)
68 patch_file_number=`cat "$config_file" | wc -l`
69 patch_file_number_1=`expr $patch_file_number - 1`
70
71 for i in `seq 0 $patch_file_number_1`
72 do
73 patch_order=`expr $i + 1`
74 patch_path=`sed -n ${patch_order}p $config_file`
75 printRed "${patch_file[i]}"
76 printBlue "$patch_order"
77 printBlue "$patch_path"
78
79 old_file=`echo $patch_path | awk '{print $1}'`
80 new_file=`echo $patch_path | awk '{print $2}'`
81
82 #if [ ! -f "$old/$old_file" ]
83 #then
84 # printRed "file:$old/$old_file doesn't exit"
85 #fi
86
87 #if [ ! -f "$new/$new_file" ]
88 #then
89 # printRed "file:$new/$new_file doesn't exit"
90 #fi
91
92 if [ "$new_file" = "" ]
93 then
94 printRed "diff -Nurw $old/$old_file /$new/$old_file"
95 diff -Nurw $old/$old_file $new/$old_file >> patch/patch-for-uboot.patch
96 else
97 printRed "diff -Nurw $old/$old_file $new/$new_file"
98 diff -Nurw $old/$old_file $new/$new_file >> patch/patch-for-uboot.patch
99 #diff -Nurw $old/$old_file $new/$new_file > patch/${patch_file[i]}.patch
100 #diff -Nurw "$old"/"$patch_path" "$new"/"$patch_path" > patch/${patch_file[i]}.patch
101 #diff -Nurw "$old"/"$patch_path" "$new"/"$patch_path" >> patch/patch-for-uboot1.1.6.patch
102 fi
103 done
104 }
105
106 fun_diff
附件：patch-uboot.config
1 board/san2440 board/EmbedSky SDRAM Setting
2 board/san2440/san2440.c board/EmbedSky/EmbedSky.c Personal Board Setting
3 include/configs/san2440.h include/configs/EmbedSky.h Personal Board Setting
4 cpu/arm920t/start.S Clock Setting,etc.
5 include/s3c24x0.h
6 cpu/arm920t/s3c24x0
7 rtc/s3c24x0_rtc.c
8 lib_arm/board.c
比较结果：patch-for-uboot.patch
给文本添加行号，awk非常好用！看来没有做不到的，只有想不到的！
awk '{print NR":"$0}' text.txt >> text_add_line.txt
或者更繁琐些(参考了网上的写法，没验证过，不过整体思路是对的)：
num=0
while read line
do
num=`expr $num + 1`
echo "$line"|sed "s/^/$num:/g" >>temp.txt
done<text ; mv temp.txt text
1:diff -Nurw sanEmbeded/u-boot-1.1.6/board/san2440/config.mk EmbedSky/u-boot-1.1.6/board/EmbedSky/config.mk
2:--- sanEmbeded/u-boot-1.1.6/board/san2440/config.mk 2009-11-30 22:42:13.000000000 +0800
3:+++ EmbedSky/u-boot-1.1.6/board/EmbedSky/config.mk 2009-08-07 17:54:00.000000000 +0800
4:@@ -3,13 +3,13 @@
5: # Gary Jennejohn, DENX Software Engineering, <[email protected]>
6: # David Mueller, ELSOFT AG, <[email protected]>
7: #
8:-# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
9:+# SAMSUNG SMDK2440 board with S3C2440X (ARM920T) cpu
10: #
11: # see http://www.samsung.com/ for more information on SAMSUNG
12: #
13:
14: #
15:-# SMDK2410 has 1 bank of 64 MB DRAM
16:+# TQ2440 has 1 bank of 64 MB DRAM
17: #
18: # 3000'0000 to 3400'0000
19: #
20:@@ -22,4 +22,5 @@
21: #
22:
23:
24:-TEXT_BASE = 0x33F80000
25:+TEXT_BASE = 0x33D80000
26:+#TEXT_BASE = 0x37D80000
27:diff -Nurw sanEmbeded/u-boot-1.1.6/board/san2440/EmbedSky.c EmbedSky/u-boot-1.1.6/board/EmbedSky/EmbedSky.c
28:--- sanEmbeded/u-boot-1.1.6/board/san2440/EmbedSky.c 1970-01-01 08:00:00.000000000 +0800
29:+++ EmbedSky/u-boot-1.1.6/board/EmbedSky/EmbedSky.c 2009-05-16 14:23:34.000000000 +0800
30:@@ -0,0 +1,92 @@
31:+/*
32:+ * (C) Copyright 2002
33:+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
34:+ * Marius Groeger <[email protected]>
35:+ *
36:+ * (C) Copyright 2002
37:+ * David Mueller, ELSOFT AG, <[email protected]>
38:+ *
39:+ * See file CREDITS for list of people who contributed to this
40:+ * project.
41:+ *
42:+ * This program is free software; you can redistribute it and/or
43:+ * modify it under the terms of the GNU General Public License as
44:+ * published by the Free Software Foundation; either version 2 of
45:+ * the License, or (at your option) any later version.
46:+ *
47:+ * This program is distributed in the hope that it will be useful,
48:+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
49:+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
50:+ * GNU General Public License for more details.
51:+ *
52:+ * You should have received a copy of the GNU General Public License
53:+ * along with this program; if not, write to the Free Software
54:+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
55:+ * MA 02111-1307 USA
56:+ */
57:+
58:+#include <common.h>
59:+#include <s3c2410.h>
60:+
61:+DECLARE_GLOBAL_DATA_PTR;
62:+
63:+
64:+/*
65:+ * Miscellaneous platform dependent initialisations
66:+ */
67:+int board_init (void)
68:+{
69:+ S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
70:+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
71:+
72:+ /* set up the I/O ports */
73:+ gpio->GPACON = 0x007FFFFF;
74:+ gpio->GPBCON = 0x00055555;
75:+ gpio->GPBUP = 0x000007FF;
76:+ gpio->GPCCON = 0xAAAAAAAA;
77:+ gpio->GPCUP = 0x0000FFFF;
78:+ gpio->GPDCON = 0xAAAAAAAA;
79:+ gpio->GPDUP = 0x0000FFFF;
80:+ gpio->GPECON = 0xAAAAAAAA;
81:+ gpio->GPEUP = 0x0000FFFF;
82:+ gpio->GPFCON = 0x000055AA;
83:+ gpio->GPFUP = 0x000000FF;
84:+ gpio->GPGCON = 0xFF94FFBA;
85:+ gpio->GPGUP = 0x0000FFEF;
86:+ gpio->GPGDAT = gpio->GPGDAT & (~(1<<4)) | (1<<4) ;
87:+ gpio->GPHCON = 0x002AFAAA;
88:+ gpio->GPHUP = 0x000007FF;
89:+ gpio->GPJCON = 0x02aaaaaa;
90:+ gpio->GPJUP = 0x00001fff;
91:+
92:+// S3C24X0_I2S * const i2s = S3C24X0_GetBase_I2S(); //HJ_add å±èœIIS,
93:+// i2s->IISCON = 0x00; //HJ_add å±èœIIS,
94:+
95:+ /* support both of S3C2410 and S3C2440, by www.embedsky.net */
96:+ if ((gpio->GSTATUS1 == 0x32410000) || (gpio->GSTATUS1 == 0x32410002))
97:+ {
98:+ /* arch number of SMDK2410-Board */
99:+ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
100:+ }
101:+ else
102:+ {
103:+ /* arch number of SMDK2440-Board */
104:+ gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
105:+ }
106:+
107:+ /* adress of boot parameters */
108:+ gd->bd->bi_boot_params = 0x30000100;
109:+
110:+ icache_enable();
111:+ dcache_enable();
112:+
113:+ return 0;
114:+}
115:+
116:+int dram_init (void)
117:+{
118:+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
119:+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
120:+
121:+ return 0;
122:+}
123:diff -Nurw sanEmbeded/u-boot-1.1.6/board/san2440/lowlevel_init.S EmbedSky/u-boot-1.1.6/board/EmbedSky/lowlevel_init.S
124:--- sanEmbeded/u-boot-1.1.6/board/san2440/lowlevel_init.S 2009-11-30 22:42:13.000000000 +0800
125:+++ EmbedSky/u-boot-1.1.6/board/EmbedSky/lowlevel_init.S 2009-08-07 13:34:28.000000000 +0800
126:@@ -51,11 +51,11 @@
127: #define WAIT (0x1<<2)
128: #define UBLB (0x1<<3)
129:
130:-#define B1_BWSCON (DW32)
131:+#define B1_BWSCON (DW16)
132: #define B2_BWSCON (DW16)
133: #define B3_BWSCON (DW16 + WAIT + UBLB)
134: #define B4_BWSCON (DW16)
135:-#define B5_BWSCON (DW16)
136:+#define B5_BWSCON (DW8)
137: #define B6_BWSCON (DW32)
138: #define B7_BWSCON (DW32)
139:
140:@@ -110,20 +110,57 @@
141: #define B5_PMC 0x0 /* normal */
142:
143: #define B6_MT 0x3 /* SDRAM */
144:+/*#define B6_Trcd 0x1 *//* 3clk */ /*HJ_del 100MHz */
145:+/*#define B6_SCAN 0x1 *//* 9bit */ /*HJ_del 64MB SDRAM */
146:+/*#define B6_Trcd 0x0 *//* 2clk */ /*HJ_del 133MHz */
147:+/*#define B6_SCAN 0x2 *//* 10bit */ /*HJ_del 128MB SDRAM */
148:+#if CONFIG_133MHZ_SDRAM
149:+#define B6_Trcd 0x0
150:+#else
151: #define B6_Trcd 0x1
152:-#define B6_SCAN 0x1 /* 9bit */
153:+#endif
154:+#if CONFIG_128MB_SDRAM
155:+#define B6_SCAN 0x2
156:+#else
157:+#define B6_SCAN 0x1
158:+#endif
159:
160: #define B7_MT 0x3 /* SDRAM */
161:-#define B7_Trcd 0x1 /* 3clk */
162:-#define B7_SCAN 0x1 /* 9bit */
163:+/*#define B7_Trcd 0x1 *//* 3clk */ /*HJ_del 100MHz */
164:+/*#define B7_SCAN 0x1 *//* 9bit */ /*HJ_del 64MB SDRAM */
165:+/*#define B7_Trcd 0x0 *//* 2clk */ /*HJ_add 133MHz */
166:+/*#define B7_SCAN 0x2 *//* 10bit */ /*HJ_del 128MB SDRAM */
167:+#if CONFIG_133MHZ_SDRAM
168:+#define B7_Trcd 0x0
169:+#else
170:+#define B7_Trcd 0x1
171:+#endif
172:+#if CONFIG_128MB_SDRAM
173:+#define B7_SCAN 0x2
174:+#else
175:+#define B7_SCAN 0x1
176:+#endif
177:
178: /* REFRESH parameter */
179: #define REFEN 0x1 /* Refresh enable */
180: #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
181:-#define Trp 0x0 /* 2clk */
182:-#define Trc 0x3 /* 7clk */
183:-#define Tchr 0x2 /* 3clk */
184:-#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
185:+/*#define Trp 0x0 *//* 2clk */ /* HJ_del 100MHz */
186:+/*#define Trc 0x3 *//* 7clk */ /* HJ_del 100MHz */
187:+/*#define Tchr 0x2 *//* 3clk */ /* HJ_del 100MHz */
188:+/*#define REFCNT 0x4f4 *//* period=7.8125us, HCLK=100Mhz, (2048+1-7.8125*100) */ /* HJ_del 100MHz */
189:+/*#define Trp 0x1 *//* 3clk */ /* HJ_del 133MHz */
190:+/*#define Tsrc 0x3 *//* 7clk */ /* HJ_del 133MHz */
191:+/*#define REFCNT 0x3f4 *//* period=7.8125us, HCLK=133Mhz, (2048+1-7.8125*133) */ /* HJ_del 133MHz */
192:+#if CONFIG_133MHZ_SDRAM
193:+#define Trp 0x1
194:+#define Tsrc 0x3
195:+#define REFCNT 0x3f4
196:+#else
197:+#define Trp 0x0
198:+#define Trc 0x3
199:+#define Tchr 0x2
200:+#define REFCNT 0x4f4
201:+#endif
202: /**************************************/
203:
204: _TEXT_BASE:
205:@@ -161,7 +198,22 @@
206: .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
207: .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
208: .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
209:+/* .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) */ /* HJ_del 100MHz */
210:+/* .word 0x32 */ /* HJ_del 100MHz */
211:+/* .word 0x30 */ /* HJ_del 100MHz */
212:+/* .word 0x30 */ /* HJ_del 100MHz */
213:+/* .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+REFCNT) */ /* HJ_del 133MHz */
214:+/* .word 0xB2 */ /* HJ_del 133MHz */
215:+/* .word 0x20 */ /* HJ_del 133MHz */
216:+/* .word 0x20 */ /* HJ_del 133MHz */
217:+#if CONFIG_133MHZ_SDRAM
218:+ .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Tsrc<<18)+REFCNT)
219:+ .word 0xB2
220:+ .word 0xB0
221:+ .word 0xB0
222:+#else
223: .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
224: .word 0x32
225: .word 0x30
226: .word 0x30
227:+#endif
228:diff -Nurw sanEmbeded/u-boot-1.1.6/board/san2440/Makefile EmbedSky/u-boot-1.1.6/board/EmbedSky/Makefile
229:--- sanEmbeded/u-boot-1.1.6/board/san2440/Makefile 2009-11-30 22:42:13.000000000 +0800
230:+++ EmbedSky/u-boot-1.1.6/board/EmbedSky/Makefile 2009-08-07 17:51:28.000000000 +0800
231:@@ -25,7 +25,7 @@
232:
233: LIB = $(obj)lib$(BOARD).a
234:
235:-COBJS := san2440.o flash.o
236:+COBJS := EmbedSky.o flash.o
237: SOBJS := lowlevel_init.o
238:
239: SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
240:diff -Nurw sanEmbeded/u-boot-1.1.6/board/san2440/san2440.c EmbedSky/u-boot-1.1.6/board/EmbedSky/san2440.c
241:--- sanEmbeded/u-boot-1.1.6/board/san2440/san2440.c 2009-11-30 22:42:13.000000000 +0800
242:+++ EmbedSky/u-boot-1.1.6/board/EmbedSky/san2440.c 1970-01-01 08:00:00.000000000 +0800
243:@@ -1,123 +0,0 @@
244:-/*
245:- * (C) Copyright 2002
246:- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
247:- * Marius Groeger <[email protected]>
248:- *
249:- * (C) Copyright 2002
250:- * David Mueller, ELSOFT AG, <[email protected]>
251:- *
252:- * See file CREDITS for list of people who contributed to this
253:- * project.
254:- *
255:- * This program is free software; you can redistribute it and/or
256:- * modify it under the terms of the GNU General Public License as
257:- * published by the Free Software Foundation; either version 2 of
258:- * the License, or (at your option) any later version.
259:- *
260:- * This program is distributed in the hope that it will be useful,
261:- * but WITHOUT ANY WARRANTY; without even the implied warranty of
262:- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
263:- * GNU General Public License for more details.
264:- *
265:- * You should have received a copy of the GNU General Public License
266:- * along with this program; if not, write to the Free Software
267:- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
268:- * MA 02111-1307 USA
269:- */
270:-
271:-#include <common.h>
272:-#include <s3c2410.h>
273:-
274:-DECLARE_GLOBAL_DATA_PTR;
275:-
276:-#define FCLK_SPEED 1
277:-
278:-#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
279:-#define M_MDIV 0xC3
280:-#define M_PDIV 0x4
281:-#define M_SDIV 0x1
282:-#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
283:-#define M_MDIV 0xA1
284:-#define M_PDIV 0x3
285:-#define M_SDIV 0x1
286:-#endif
287:-
288:-#define USB_CLOCK 1
289:-
290:-#if USB_CLOCK==0
291:-#define U_M_MDIV 0xA1
292:-#define U_M_PDIV 0x3
293:-#define U_M_SDIV 0x1
294:-#elif USB_CLOCK==1
295:-#define U_M_MDIV 0x48
296:-#define U_M_PDIV 0x3
297:-#define U_M_SDIV 0x2
298:-#endif
299:-
300:-static inline void delay (unsigned long loops)
301:-{
302:- __asm__ volatile ("1:/n"
303:- "subs %0, %1, #1/n"
304:- "bne 1b":"=r" (loops):"0" (loops));
305:-}
306:-
307:-/*
308:- * Miscellaneous platform dependent initialisations
309:- */
310:-
311:-int board_init (void)
312:-{
313:- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
314:- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
315:-
316:- /* to reduce PLL lock time, adjust the LOCKTIME register */
317:- clk_power->LOCKTIME = 0xFFFFFF;
318:-
319:- /* configure MPLL */
320:- clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
321:-
322:- /* some delay between MPLL and UPLL */
323:- delay (4000);
324:-
325:- /* configure UPLL */
326:- clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
327:-
328:- /* some delay between MPLL and UPLL */
329:- delay (8000);
330:-
331:- /* set up the I/O ports */
332:- gpio->GPACON = 0x007FFFFF;
333:- gpio->GPBCON = 0x00044555;
334:- gpio->GPBUP = 0x000007FF;
335:- gpio->GPCCON = 0xAAAAAAAA;
336:- gpio->GPCUP = 0x0000FFFF;
337:- gpio->GPDCON = 0xAAAAAAAA;
338:- gpio->GPDUP = 0x0000FFFF;
339:- gpio->GPECON = 0xAAAAAAAA;
340:- gpio->GPEUP = 0x0000FFFF;
341:- gpio->GPFCON = 0x000055AA;
342:- gpio->GPFUP = 0x000000FF;
343:- gpio->GPGCON = 0xFF95FFBA;
344:- gpio->GPGUP = 0x0000FFFF;
345:- gpio->GPHCON = 0x002AFAAA;
346:- gpio->GPHUP = 0x000007FF;
347:-
348:- /* arch number of SMDK2410-Board */
349:- gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
350:-
351:- /* adress of boot parameters */
352:- gd->bd->bi_boot_params = 0x30000100;
353:-
354:- icache_enable();
355:- dcache_enable();
356:-
357:- return 0;
358:-}
359:-
360:-int dram_init (void)
361:-{
362:- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
363:- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
364:-
365:- return 0;
366:-}
367:diff -Nurw sanEmbeded/u-boot-1.1.6/board/san2440/u-boot.lds EmbedSky/u-boot-1.1.6/board/EmbedSky/u-boot.lds
368:--- sanEmbeded/u-boot-1.1.6/board/san2440/u-boot.lds 2009-11-30 22:42:13.000000000 +0800
369:+++ EmbedSky/u-boot-1.1.6/board/EmbedSky/u-boot.lds 2009-08-07 17:53:46.000000000 +0800
370:@@ -33,6 +33,7 @@
371: .text :
372: {
373: cpu/arm920t/start.o (.text)
374:+ modules/nand_read.module (.text)
375: *(.text)
376: }
377:
378:--- sanEmbeded/u-boot-1.1.6/board/san2440/san2440.c 2009-11-30 22:42:13.000000000 +0800
379:+++ EmbedSky/u-boot-1.1.6/board/EmbedSky/EmbedSky.c 2009-05-16 14:23:34.000000000 +0800
380:@@ -30,64 +30,18 @@
381:
382: DECLARE_GLOBAL_DATA_PTR;
383:
384:-#define FCLK_SPEED 1
385:-
386:-#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
387:-#define M_MDIV 0xC3
388:-#define M_PDIV 0x4
389:-#define M_SDIV 0x1
390:-#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
391:-#define M_MDIV 0xA1
392:-#define M_PDIV 0x3
393:-#define M_SDIV 0x1
394:-#endif
395:-
396:-#define USB_CLOCK 1
397:-
398:-#if USB_CLOCK==0
399:-#define U_M_MDIV 0xA1
400:-#define U_M_PDIV 0x3
401:-#define U_M_SDIV 0x1
402:-#elif USB_CLOCK==1
403:-#define U_M_MDIV 0x48
404:-#define U_M_PDIV 0x3
405:-#define U_M_SDIV 0x2
406:-#endif
407:-
408:-static inline void delay (unsigned long loops)
409:-{
410:- __asm__ volatile ("1:/n"
411:- "subs %0, %1, #1/n"
412:- "bne 1b":"=r" (loops):"0" (loops));
413:-}
414:
415: /*
416: * Miscellaneous platform dependent initialisations
417: */
418:-
419: int board_init (void)
420: {
421: S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
422: S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
423:
424:- /* to reduce PLL lock time, adjust the LOCKTIME register */
425:- clk_power->LOCKTIME = 0xFFFFFF;
426:-
427:- /* configure MPLL */
428:- clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
429:-
430:- /* some delay between MPLL and UPLL */
431:- delay (4000);
432:-
433:- /* configure UPLL */
434:- clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
435:-
436:- /* some delay between MPLL and UPLL */
437:- delay (8000);
438:-
439: /* set up the I/O ports */
440: gpio->GPACON = 0x007FFFFF;
441:- gpio->GPBCON = 0x00044555;
442:+ gpio->GPBCON = 0x00055555;
443: gpio->GPBUP = 0x000007FF;
444: gpio->GPCCON = 0xAAAAAAAA;
445: gpio->GPCUP = 0x0000FFFF;
446:@@ -97,13 +51,28 @@
447: gpio->GPEUP = 0x0000FFFF;
448: gpio->GPFCON = 0x000055AA;
449: gpio->GPFUP = 0x000000FF;
450:- gpio->GPGCON = 0xFF95FFBA;
451:- gpio->GPGUP = 0x0000FFFF;
452:+ gpio->GPGCON = 0xFF94FFBA;
453:+ gpio->GPGUP = 0x0000FFEF;
454:+ gpio->GPGDAT = gpio->GPGDAT & (~(1<<4)) | (1<<4) ;
455: gpio->GPHCON = 0x002AFAAA;
456: gpio->GPHUP = 0x000007FF;
457:+ gpio->GPJCON = 0x02aaaaaa;
458:+ gpio->GPJUP = 0x00001fff;
459:
460:+// S3C24X0_I2S * const i2s = S3C24X0_GetBase_I2S(); //HJ_add å±èœIIS,
461:+// i2s->IISCON = 0x00; //HJ_add å±èœIIS,
462:+
463:+ /* support both of S3C2410 and S3C2440, by www.embedsky.net */
464:+ if ((gpio->GSTATUS1 == 0x32410000) || (gpio->GSTATUS1 == 0x32410002))
465:+ {
466: /* arch number of SMDK2410-Board */
467: gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
468:+ }
469:+ else
470:+ {
471:+ /* arch number of SMDK2440-Board */
472:+ gd->bd->bi_arch_number = MACH_TYPE_S3C2440;
473:+ }
474:
475: /* adress of boot parameters */
476: gd->bd->bi_boot_params = 0x30000100;
477:--- sanEmbeded/u-boot-1.1.6/include/configs/san2440.h 2006-11-02 22:15:01.000000000 +0800
478:+++ EmbedSky/u-boot-1.1.6/include/configs/EmbedSky.h 2009-08-24 14:46:02.000000000 +0800
479:@@ -38,11 +38,38 @@
480: #define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
481:
482: /* input clock of PLL */
483:-#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
484:-
485:+#define CONFIG_SYS_CLK_FREQ 12000000/* the TQ2440 has 12MHz input clock */
486:+//#define CONFIG_SYS_CLK_FREQ 16934400 /* the SMDK2410 has 12MHz input clock */
487:
488: #define USE_920T_MMU 1
489:-#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
490:+
491:+#define CONFIG_USB_DEVICE 1
492:+
493:+#ifdef CONFIG_USB_DEVICE
494:+#define CONFIG_USE_IRQ 1
495:+#endif
496:+
497:+#define CONFIG_64MB_Nand 0 //æ·»å äºå¯¹64MB Nand Flashæ¯æ
498:+#define CONFIG_128MB_Nand 0 //æ·»å äºå¯¹128MB Nand Flashæ¯æïŒåœäžº1æ¶å°±æ¯128MBçNand Flash
499:+
500:+/* enable 128MB SDRAM */
501:+#define CONFIG_128MB_SDRAM 0
502:+
503:+/* enable SDRAM 133MHz */
504:+#define CONFIG_133MHZ_SDRAM 0
505:+
506:+#define CONFIG_JFFS2_CMDLINE 1
507:+#define CONFIG_JFFS2_NAND 1
508:+
509:+#define MTDIDS_DEFAULT "nand0=nandflash0"
510:+
511:+#define MTDPARTS_DEFAULT "mtdparts=nandflash0:256k@0(bios)," /
512:+ "128k(params)," /
513:+ "128k(toc)," /
514:+ "512k(eboot)," /
515:+ "1024k(logo)," /
516:+ "2m(kernel)," /
517:+ "-(root)"
518:
519: /*
520: * Size of malloc() pool
521:@@ -53,9 +80,11 @@
522: /*
523: * Hardware drivers
524: */
525:-#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
526:-#define CS8900_BASE 0x19000300
527:-#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
528:+#define CONFIG_DRIVER_DM9000 1
529:+#define CONFIG_DM9000_BASE 0x20000300
530:+#define DM9000_IO CONFIG_DM9000_BASE
531:+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
532:+#define CONFIG_DM9000_USE_16BIT
533:
534: /*
535: * select serial console configuration
536:@@ -67,36 +96,121 @@
537: ************************************************************/
538: #define CONFIG_RTC_S3C24X0 1
539:
540:+/* enable EmbedSky Logo */
541:+#define CONFIG_EMBEDSKY_LOGO 1
542:+
543:+/* set LCD params */
544:+#ifdef CONFIG_EMBEDSKY_LOGO
545:+
546:+#define TFT800600 1
547:+#define TFT800480 2
548:+#define VGA 3
549:+#define TFT480272 4
550:+#define TFT240320 5
551:+#define W35 6
552:+
553:+#define LCD_TFT W35
554:+
555:+#if(LCD_TFT == W35)
556:+#define CONFIG_EMBEDSKY_LCD_VBPD 12
557:+#define CONFIG_EMBEDSKY_LCD_VFPD 4
558:+#define CONFIG_EMBEDSKY_LCD_VSPW 5
559:+#define CONFIG_EMBEDSKY_LCD_HBPD 21
560:+#define CONFIG_EMBEDSKY_LCD_HFPD 32
561:+#define CONFIG_EMBEDSKY_LCD_HSPW 44
562:+#define CONFIG_EMBEDSKY_LCD_CLKVAL 6
563:+
564:+#elif(LCD_TFT == TFT240320)
565:+#define CONFIG_EMBEDSKY_LCD_VBPD 1
566:+#define CONFIG_EMBEDSKY_LCD_VFPD 2
567:+#define CONFIG_EMBEDSKY_LCD_VSPW 1
568:+#define CONFIG_EMBEDSKY_LCD_HBPD 6
569:+#define CONFIG_EMBEDSKY_LCD_HFPD 3
570:+#define CONFIG_EMBEDSKY_LCD_HSPW 1
571:+#define CONFIG_EMBEDSKY_LCD_CLKVAL 2
572:+
573:+#elif(LCD_TFT == TFT480272)
574:+#define CONFIG_EMBEDSKY_LCD_VBPD 3
575:+#define CONFIG_EMBEDSKY_LCD_VFPD 5
576:+#define CONFIG_EMBEDSKY_LCD_VSPW 5
577:+#define CONFIG_EMBEDSKY_LCD_HBPD 5
578:+#define CONFIG_EMBEDSKY_LCD_HFPD 15
579:+#define CONFIG_EMBEDSKY_LCD_HSPW 8
580:+#define CONFIG_EMBEDSKY_LCD_CLKVAL 7
581:+
582:+#elif(LCD_TFT == VGA)
583:+#define CONFIG_EMBEDSKY_LCD_VBPD 29
584:+#define CONFIG_EMBEDSKY_LCD_VFPD 5
585:+#define CONFIG_EMBEDSKY_LCD_VSPW 4
586:+#define CONFIG_EMBEDSKY_LCD_HBPD 71
587:+#define CONFIG_EMBEDSKY_LCD_HFPD 40
588:+#define CONFIG_EMBEDSKY_LCD_HSPW 31
589:+#define CONFIG_EMBEDSKY_LCD_CLKVAL 1
590:+
591:+#elif(LCD_TFT == TFT800480)
592:+#define CONFIG_EMBEDSKY_LCD_VBPD 4
593:+#define CONFIG_EMBEDSKY_LCD_VFPD 2
594:+#define CONFIG_EMBEDSKY_LCD_VSPW 2
595:+#define CONFIG_EMBEDSKY_LCD_HBPD 27
596:+#define CONFIG_EMBEDSKY_LCD_HFPD 14
597:+#define CONFIG_EMBEDSKY_LCD_HSPW 8
598:+#define CONFIG_EMBEDSKY_LCD_CLKVAL 2
599:+
600:+#elif(LCD_TFT == TFT800600)
601:+#define CONFIG_EMBEDSKY_LCD_VBPD 4
602:+#define CONFIG_EMBEDSKY_LCD_VFPD 2
603:+#define CONFIG_EMBEDSKY_LCD_VSPW 2
604:+#define CONFIG_EMBEDSKY_LCD_HBPD 27
605:+#define CONFIG_EMBEDSKY_LCD_HFPD 14
606:+#define CONFIG_EMBEDSKY_LCD_HSPW 8
607:+#define CONFIG_EMBEDSKY_LCD_CLKVAL 2
608:+
609:+#endif
610:+#endif
611:+
612: /* allow to overwrite serial and ethaddr */
613: #define CONFIG_ENV_OVERWRITE
614:
615: #define CONFIG_BAUDRATE 115200
616:
617:+/* for tag(s) to transfer message to kernel, www.embedsky.net */
618:+#define CONFIG_SETUP_MEMORY_TAGS 1
619:+#define CONFIG_CMDLINE_TAG 1
620:+
621: /***********************************************************
622: * Command definition
623: ***********************************************************/
624: #define CONFIG_COMMANDS /
625: (CONFIG_CMD_DFL | /
626: CFG_CMD_CACHE | /
627:- /*CFG_CMD_NAND |*/ /
628:+ /* Start: by www.embedsky.net */ /
629:+ CFG_CMD_PING | /
630:+ CFG_CMD_JFFS2 | /
631:+ CFG_CMD_NAND | /
632:+ /* End: by www.embedsky.net */ /
633: /*CFG_CMD_EEPROM |*/ /
634: /*CFG_CMD_I2C |*/ /
635: /*CFG_CMD_USB |*/ /
636: CFG_CMD_REGINFO | /
637:- CFG_CMD_DATE | /
638:- CFG_CMD_ELF)
639:+ CFG_CMD_ELF | /
640:+ CFG_CMD_DATE)
641:
642: /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
643: #include <cmd_confdefs.h>
644:
645:-#define CONFIG_BOOTDELAY 3
646:-/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
647:-/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */
648:+#define CONFIG_BOOTDELAY 0
649:+
650:+#if CONFIG_128MB_SDRAM
651:+#define CONFIG_BOOTARGS "noinitrd root=/dev/mtdblock2 init=/linuxrc console=ttySAC0 mem=128M"
652:+#else
653:+#define CONFIG_BOOTARGS "noinitrd root=/dev/mtdblock2 init=/linuxrc console=ttySAC0"
654:+#endif
655:+#define CONFIG_ETHADDR 0a:1b:2c:3d:4e:5f
656: #define CONFIG_NETMASK 255.255.255.0
657:-#define CONFIG_IPADDR 10.0.0.110
658:-#define CONFIG_SERVERIP 10.0.0.1
659:+#define CONFIG_IPADDR 192.168.1.6
660:+#define CONFIG_SERVERIP 192.168.1.8
661: /*#define CONFIG_BOOTFILE "elinos-lart" */
662:-/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
663:+#define CONFIG_BOOTCOMMAND "nboot 0x32000000 kernel; bootm 0x32000000"
664:
665: #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
666: #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
667:@@ -108,18 +222,26 @@
668: * Miscellaneous configurable options
669: */
670: #define CFG_LONGHELP /* undef to save memory */
671:-#define CFG_PROMPT "SMDK2410 # " /* Monitor Command Prompt */
672:+#define CFG_PROMPT "EmbedSky> " /* Monitor Command Prompt */
673: #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
674: #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
675: #define CFG_MAXARGS 16 /* max number of command args */
676: #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
677:
678: #define CFG_MEMTEST_START 0x30000000 /* memtest works on */
679:+#ifdef CONFIG_128MB_SDRAM
680:+#define CFG_MEMTEST_END 0x37F00000 /* 127 MB in DRAM */
681:+#else
682: #define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
683:+#endif
684:
685: #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
686:
687:+#ifdef CONFIG_128MB_SDRAM
688:+#define CFG_LOAD_ADDR 0x37000000 /* default load address */
689:+#else
690: #define CFG_LOAD_ADDR 0x33000000 /* default load address */
691:+#endif
692:
693: /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
694: /* it to wrap 100 times (total 1562500) to get 1 sec. */
695:@@ -144,26 +266,34 @@
696: */
697: #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
698: #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
699:+#if CONFIG_128MB_SDRAM
700:+#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
701:+#else
702: #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
703:+#endif
704:
705: #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
706:
707: #define CFG_FLASH_BASE PHYS_FLASH_1
708:
709:+#if CONFIG_64MB_Nand
710:+#define CONFIG_SURPORT_WINCE 1 //å 䞺ç°åšè¿äžæ¯æ2K页é¢çwince
711:+#endif
712:+
713: /*-----------------------------------------------------------------------
714: * FLASH and environment organization
715: */
716:
717:-#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
718: #if 0
719:-#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
720:+#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
721: #endif
722:+#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
723:
724: #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
725: #ifdef CONFIG_AMD_LV800
726:-#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
727:+#define PHYS_FLASH_SIZE 0x00200000 /* 1MB */
728: #define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
729:-#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
730:+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x1F0000) /* addr of environment */
731: #endif
732: #ifdef CONFIG_AMD_LV400
733: #define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
734:@@ -175,7 +305,17 @@
735: #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
736: #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
737:
738:-#define CFG_ENV_IS_IN_FLASH 1
739:-#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
740:+//#define CFG_ENV_IS_IN_FLASH 1
741:+#define CFG_ENV_IS_IN_NAND 1
742:+#define CFG_ENV_OFFSET 0x40000
743:+#define CFG_ENV_SIZE64 0xc000 /* Total Size of Environment Sector */
744:+#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
745:+
746:+/*-----------------------------------------------------------------------
747:+ * NAND flash settings
748:+ */
749:+#define CFG_NAND_BASE 0
750:+#define CFG_MAX_NAND_DEVICE 1
751:+#define NAND_MAX_CHIPS 1
752:
753: #endif /* __CONFIG_H */
754:--- sanEmbeded/u-boot-1.1.6/cpu/arm920t/start.S 2006-11-02 22:15:01.000000000 +0800
755:+++ EmbedSky/u-boot-1.1.6/Clock 1970-01-01 08:00:00.000000000 +0800
756:@@ -1,434 +0,0 @@
757:-/*
758:- * armboot - Startup Code for ARM920 CPU-core
759:- *
760:- * Copyright (c) 2001 Marius Gröger <[email protected]>
761:- * Copyright (c) 2002 Alex Züpke <[email protected]>
762:- * Copyright (c) 2002 Gary Jennejohn <[email protected]>
763:- *
764:- * See file CREDITS for list of people who contributed to this
765:- * project.
766:- *
767:- * This program is free software; you can redistribute it and/or
768:- * modify it under the terms of the GNU General Public License as
769:- * published by the Free Software Foundation; either version 2 of
770:- * the License, or (at your option) any later version.
771:- *
772:- * This program is distributed in the hope that it will be useful,
773:- * but WITHOUT ANY WARRANTY; without even the implied warranty of
774:- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
775:- * GNU General Public License for more details.
776:- *
777:- * You should have received a copy of the GNU General Public License
778:- * along with this program; if not, write to the Free Software
779:- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
780:- * MA 02111-1307 USA
781:- */
782:-
783:-
784:-#include <config.h>
785:-#include <version.h>
786:-
787:-
788:-/*
789:- *************************************************************************
790:- *
791:- * Jump vector table as in table 3.1 in [1]
792:- *
793:- *************************************************************************
794:- */
795:-
796:-
797:-.globl _start
798:-_start: b reset
799:- ldr pc, _undefined_instruction
800:- ldr pc, _software_interrupt
801:- ldr pc, _prefetch_abort
802:- ldr pc, _data_abort
803:- ldr pc, _not_used
804:- ldr pc, _irq
805:- ldr pc, _fiq
806:-
807:-_undefined_instruction: .word undefined_instruction
808:-_software_interrupt: .word software_interrupt
809:-_prefetch_abort: .word prefetch_abort
810:-_data_abort: .word data_abort
811:-_not_used: .word not_used
812:-_irq: .word irq
813:-_fiq: .word fiq
814:-
815:- .balignl 16,0xdeadbeef
816:-
817:-
818:-/*
819:- *************************************************************************
820:- *
821:- * Startup Code (reset vector)
822:- *
823:- * do important init only if we don't start from memory!
824:- * relocate armboot to ram
825:- * setup stack
826:- * jump to second stage
827:- *
828:- *************************************************************************
829:- */
830:-
831:-_TEXT_BASE:
832:- .word TEXT_BASE
833:-
834:-.globl _armboot_start
835:-_armboot_start:
836:- .word _start
837:-
838:-/*
839:- * These are defined in the board-specific linker script.
840:- */
841:-.globl _bss_start
842:-_bss_start:
843:- .word __bss_start
844:-
845:-.globl _bss_end
846:-_bss_end:
847:- .word _end
848:-
849:-#ifdef CONFIG_USE_IRQ
850:-/* IRQ stack memory (calculated at run-time) */
851:-.globl IRQ_STACK_START
852:-IRQ_STACK_START:
853:- .word 0x0badc0de
854:-
855:-/* IRQ stack memory (calculated at run-time) */
856:-.globl FIQ_STACK_START
857:-FIQ_STACK_START:
858:- .word 0x0badc0de
859:-#endif
860:-
861:-
862:-/*
863:- * the actual reset code
864:- */
865:-
866:-reset:
867:- /*
868:- * set the cpu to SVC32 mode
869:- */
870:- mrs r0,cpsr
871:- bic r0,r0,#0x1f
872:- orr r0,r0,#0xd3
873:- msr cpsr,r0
874:-
875:-/* turn off the watchdog */
876:-#if defined(CONFIG_S3C2400)
877:-# define pWTCON 0x15300000
878:-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
879:-# define CLKDIVN 0x14800014 /* clock divisor register */
880:-#elif defined(CONFIG_S3C2410)
881:-# define pWTCON 0x53000000
882:-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
883:-# define INTSUBMSK 0x4A00001C
884:-# define CLKDIVN 0x4C000014 /* clock divisor register */
885:-#endif
886:-
887:-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
888:- ldr r0, =pWTCON
889:- mov r1, #0x0
890:- str r1, [r0]
891:-
892:- /*
893:- * mask all IRQs by setting all bits in the INTMR - default
894:- */
895:- mov r1, #0xffffffff
896:- ldr r0, =INTMSK
897:- str r1, [r0]
898:-# if defined(CONFIG_S3C2410)
899:- ldr r1, =0x3ff
900:- ldr r0, =INTSUBMSK
901:- str r1, [r0]
902:-# endif
903:-
904:- /* FCLK:HCLK:PCLK = 1:2:4 */
905:- /* default FCLK is 120 MHz ! */
906:- ldr r0, =CLKDIVN
907:- mov r1, #3
908:- str r1, [r0]
909:-#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
910:-
911:- /*
912:- * we do sys-critical inits only at reboot,
913:- * not when booting from ram!
914:- */
915:-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
916:- bl cpu_init_crit
917:-#endif
918:-
919:-#ifndef CONFIG_SKIP_RELOCATE_UBOOT
920:-relocate: /* relocate U-Boot to RAM */
921:- adr r0, _start /* r0 <- current position of code */
922:- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
923:- cmp r0, r1 /* don't reloc during debug */
924:- beq stack_setup
925:-
926:- ldr r2, _armboot_start
927:- ldr r3, _bss_start
928:- sub r2, r3, r2 /* r2 <- size of armboot */
929:- add r2, r0, r2 /* r2 <- source end address */
930:-
931:-copy_loop:
932:- ldmia r0!, {r3-r10} /* copy from source address [r0] */
933:- stmia r1!, {r3-r10} /* copy to target address [r1] */
934:- cmp r0, r2 /* until source end addreee [r2] */
935:- ble copy_loop
936:-#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
937:-
938:- /* Set up the stack */
939:-stack_setup:
940:- ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
941:- sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
942:- sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
943:-#ifdef CONFIG_USE_IRQ
944:- sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
945:-#endif
946:- sub sp, r0, #12 /* leave 3 words for abort-stack */
947:-
948:-clear_bss:
949:- ldr r0, _bss_start /* find start of bss segment */
950:- ldr r1, _bss_end /* stop here */
951:- mov r2, #0x00000000 /* clear */
952:-
953:-clbss_l:str r2, [r0] /* clear loop... */
954:- add r0, r0, #4
955:- cmp r0, r1
956:- ble clbss_l
957:-
958:-#if 0
959:- /* try doing this stuff after the relocation */
960:- ldr r0, =pWTCON
961:- mov r1, #0x0
962:- str r1, [r0]
963:-
964:- /*
965:- * mask all IRQs by setting all bits in the INTMR - default
966:- */
967:- mov r1, #0xffffffff
968:- ldr r0, =INTMR
969:- str r1, [r0]
970:-
971:- /* FCLK:HCLK:PCLK = 1:2:4 */
972:- /* default FCLK is 120 MHz ! */
973:- ldr r0, =CLKDIVN
974:- mov r1, #3
975:- str r1, [r0]
976:- /* END stuff after relocation */
977:-#endif
978:-
979:- ldr pc, _start_armboot
980:-
981:-_start_armboot: .word start_armboot
982:-
983:-
984:-/*
985:- *************************************************************************
986:- *
987:- * CPU_init_critical registers
988:- *
989:- * setup important registers
990:- * setup memory timing
991:- *
992:- *************************************************************************
993:- */
994:-
995:-
996:-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
997:-cpu_init_crit:
998:- /*
999:- * flush v4 I/D caches
1000:- */
1001:- mov r0, #0
1002:- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
1003:- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
1004:-
1005:- /*
1006:- * disable MMU stuff and caches
1007:- */
1008:- mrc p15, 0, r0, c1, c0, 0
1009:- bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
1010:- bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
1011:- orr r0, r0, #0x00000002 @ set bit 2 (A) Align
1012:- orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
1013:- mcr p15, 0, r0, c1, c0, 0
1014:-
1015:- /*
1016:- * before relocating, we have to setup RAM timing
1017:- * because memory timing is board-dependend, you will
1018:- * find a lowlevel_init.S in your board directory.
1019:- */
1020:- mov ip, lr
1021:- bl lowlevel_init
1022:- mov lr, ip
1023:- mov pc, lr
1024:-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
1025:-
1026:-/*
1027:- *************************************************************************
1028:- *
1029:- * Interrupt handling
1030:- *
1031:- *************************************************************************
1032:- */
1033:-
1034:-@
1035:-@ IRQ stack frame.
1036:-@
1037:-#define S_FRAME_SIZE 72
1038:-
1039:-#define S_OLD_R0 68
1040:-#define S_PSR 64
1041:-#define S_PC 60
1042:-#define S_LR 56
1043:-#define S_SP 52
1044:-
1045:-#define S_IP 48
1046:-#define S_FP 44
1047:-#define S_R10 40
1048:-#define S_R9 36
1049:-#define S_R8 32
1050:-#define S_R7 28
1051:-#define S_R6 24
1052:-#define S_R5 20
1053:-#define S_R4 16
1054:-#define S_R3 12
1055:-#define S_R2 8
1056:-#define S_R1 4
1057:-#define S_R0 0
1058:-
1059:-#define MODE_SVC 0x13
1060:-#define I_BIT 0x80
1061:-
1062:-/*
1063:- * use bad_save_user_regs for abort/prefetch/undef/swi ...
1064:- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
1065:- */
1066:-
1067:- .macro bad_save_user_regs
1068:- sub sp, sp, #S_FRAME_SIZE
1069:- stmia sp, {r0 - r12} @ Calling r0-r12
1070:- ldr r2, _armboot_start
1071:- sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
1072:- sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
1073:- ldmia r2, {r2 - r3} @ get pc, cpsr
1074:- add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
1075:-
1076:- add r5, sp, #S_SP
1077:- mov r1, lr
1078:- stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
1079:- mov r0, sp
1080:- .endm
1081:-
1082:- .macro irq_save_user_regs
1083:- sub sp, sp, #S_FRAME_SIZE
1084:- stmia sp, {r0 - r12} @ Calling r0-r12
1085:- add r8, sp, #S_PC
1086:- stmdb r8, {sp, lr}^ @ Calling SP, LR
1087:- str lr, [r8, #0] @ Save calling PC
1088:- mrs r6, spsr
1089:- str r6, [r8, #4] @ Save CPSR
1090:- str r0, [r8, #8] @ Save OLD_R0
1091:- mov r0, sp
1092:- .endm
1093:-
1094:- .macro irq_restore_user_regs
1095:- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
1096:- mov r0, r0
1097:- ldr lr, [sp, #S_PC] @ Get PC
1098:- add sp, sp, #S_FRAME_SIZE
1099:- subs pc, lr, #4 @ return & move spsr_svc into cpsr
1100:- .endm
1101:-
1102:- .macro get_bad_stack
1103:- ldr r13, _armboot_start @ setup our mode stack
1104:- sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
1105:- sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
1106:-
1107:- str lr, [r13] @ save caller lr / spsr
1108:- mrs lr, spsr
1109:- str lr, [r13, #4]
1110:-
1111:- mov r13, #MODE_SVC @ prepare SVC-Mode
1112:- @ msr spsr_c, r13
1113:- msr spsr, r13
1114:- mov lr, pc
1115:- movs pc, lr
1116:- .endm
1117:-
1118:- .macro get_irq_stack @ setup IRQ stack
1119:- ldr sp, IRQ_STACK_START
1120:- .endm
1121:-
1122:- .macro get_fiq_stack @ setup FIQ stack
1123:- ldr sp, FIQ_STACK_START
1124:- .endm
1125:-
1126:-/*
1127:- * exception handlers
1128:- */
1129:- .align 5
1130:-undefined_instruction:
1131:- get_bad_stack
1132:- bad_save_user_regs
1133:- bl do_undefined_instruction
1134:-
1135:- .align 5
1136:-software_interrupt:
1137:- get_bad_stack
1138:- bad_save_user_regs
1139:- bl do_software_interrupt
1140:-
1141:- .align 5
1142:-prefetch_abort:
1143:- get_bad_stack
1144:- bad_save_user_regs
1145:- bl do_prefetch_abort
1146:-
1147:- .align 5
1148:-data_abort:
1149:- get_bad_stack
1150:- bad_save_user_regs
1151:- bl do_data_abort
1152:-
1153:- .align 5
1154:-not_used:
1155:- get_bad_stack
1156:- bad_save_user_regs
1157:- bl do_not_used
1158:-
1159:-#ifdef CONFIG_USE_IRQ
1160:-
1161:- .align 5
1162:-irq:
1163:- get_irq_stack
1164:- irq_save_user_regs
1165:- bl do_irq
1166:- irq_restore_user_regs
1167:-
1168:- .align 5
1169:-fiq:
1170:- get_fiq_stack
1171:- /* someone ought to write a more effiction fiq_save_user_regs */
1172:- irq_save_user_regs
1173:- bl do_fiq
1174:- irq_restore_user_regs
1175:-
1176:-#else
1177:-
1178:- .align 5
1179:-irq:
1180:- get_bad_stack
1181:- bad_save_user_regs
1182:- bl do_irq
1183:-
1184:- .align 5
1185:-fiq:
1186:- get_bad_stack
1187:- bad_save_user_regs
1188:- bl do_fiq
1189:-
1190:-#endif
1191:--- sanEmbeded/u-boot-1.1.6/include/s3c24x0.h 2006-11-02 22:15:01.000000000 +0800
1192:+++ EmbedSky/u-boot-1.1.6/include/s3c24x0.h 2008-07-14 22:42:00.000000000 +0800
1193:@@ -126,6 +126,7 @@
1194: S3C24X0_REG32 CLKCON;
1195: S3C24X0_REG32 CLKSLOW;
1196: S3C24X0_REG32 CLKDIVN;
1197:+ S3C24X0_REG32 CAMDIVN; /* for s3c2440, by www.embedsky.net */
1198: } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
1199:
1200:
1201:@@ -164,6 +165,25 @@
1202: S3C24X0_REG32 NFECC;
1203: } /*__attribute__((__packed__))*/ S3C2410_NAND;
1204:
1205:+/* NAND FLASH (see S3C2440 manual chapter 6, www.embedsky.net) */
1206:+typedef struct {
1207:+ S3C24X0_REG32 NFCONF;
1208:+ S3C24X0_REG32 NFCONT;
1209:+ S3C24X0_REG32 NFCMD;
1210:+ S3C24X0_REG32 NFADDR;
1211:+ S3C24X0_REG32 NFDATA;
1212:+ S3C24X0_REG32 NFMECCD0;
1213:+ S3C24X0_REG32 NFMECCD1;
1214:+ S3C24X0_REG32 NFSECCD;
1215:+ S3C24X0_REG32 NFSTAT;
1216:+ S3C24X0_REG32 NFESTAT0;
1217:+ S3C24X0_REG32 NFESTAT1;
1218:+ S3C24X0_REG32 NFMECC0;
1219:+ S3C24X0_REG32 NFMECC1;
1220:+ S3C24X0_REG32 NFSECC;
1221:+ S3C24X0_REG32 NFSBLK;
1222:+ S3C24X0_REG32 NFEBLK;
1223:+} /*__attribute__((__packed__))*/ S3C2440_NAND;
1224:
1225: /* UART (see manual chapter 11) */
1226: typedef struct {
1227:@@ -302,13 +322,13 @@
1228: S3C24X0_REG8 INDEX_REG;
1229: S3C24X0_REG8 res9[7];
1230: S3C24X0_REG8 MAXP_REG;
1231:- S3C24X0_REG8 res10[7];
1232:+ S3C24X0_REG8 res10[3];
1233: S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
1234: S3C24X0_REG8 res11[3];
1235: S3C24X0_REG8 IN_CSR2_REG;
1236:- S3C24X0_REG8 res12[3];
1237:+ S3C24X0_REG8 res12[7];
1238: S3C24X0_REG8 OUT_CSR1_REG;
1239:- S3C24X0_REG8 res13[7];
1240:+ S3C24X0_REG8 res13[3];
1241: S3C24X0_REG8 OUT_CSR2_REG;
1242: S3C24X0_REG8 res14[3];
1243: S3C24X0_REG8 OUT_FIFO_CNT1_REG;
1244:@@ -316,8 +336,14 @@
1245: S3C24X0_REG8 OUT_FIFO_CNT2_REG;
1246: S3C24X0_REG8 res16[3];
1247: #endif /* __BIG_ENDIAN */
1248:+ S3C24X0_REG32 res17[8];
1249: S3C24X0_USB_DEV_FIFOS fifo[5];
1250:- S3C24X0_USB_DEV_DMAS dma[5];
1251:+ S3C24X0_REG32 res18[11];
1252:+ S3C24X0_USB_DEV_DMAS ep1;
1253:+ S3C24X0_USB_DEV_DMAS ep2;
1254:+ S3C24X0_REG8 res19[16];
1255:+ S3C24X0_USB_DEV_DMAS ep3;
1256:+ S3C24X0_USB_DEV_DMAS ep4;
1257: } /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
1258:
1259:
1260:@@ -450,6 +476,12 @@
1261: S3C24X0_REG32 GSTATUS2;
1262: S3C24X0_REG32 GSTATUS3;
1263: S3C24X0_REG32 GSTATUS4;
1264:+
1265:+ /* s3c2440 */
1266:+ S3C24X0_REG32 res9[4];
1267:+ S3C24X0_REG32 GPJCON;
1268:+ S3C24X0_REG32 GPJDAT;
1269:+ S3C24X0_REG32 GPJUP;
1270: #endif
1271: } /*__attribute__((__packed__))*/ S3C24X0_GPIO;
1272:
1273:diff -Nurw sanEmbeded/u-boot-1.1.6/cpu/arm920t/s3c24x0/interrupts.c EmbedSky/u-boot-1.1.6/cpu/arm920t/s3c24x0/interrupts.c
1274:--- sanEmbeded/u-boot-1.1.6/cpu/arm920t/s3c24x0/interrupts.c 2006-11-02 22:15:01.000000000 +0800
1275:+++ EmbedSky/u-boot-1.1.6/cpu/arm920t/s3c24x0/interrupts.c 2009-03-08 23:11:56.000000000 +0800
1276:@@ -52,6 +52,7 @@
1277: static ulong timestamp;
1278: static ulong lastdec;
1279:
1280:+
1281: int interrupt_init (void)
1282: {
1283: S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
1284:@@ -216,4 +217,125 @@
1285: /*NOTREACHED*/
1286: }
1287:
1288:+/* Start : add by www.embedsky.net */
1289:+void (*isr_handle_array[50])(void);
1290:+S3C24X0_INTERRUPT * intregs;
1291:+
1292:+extern void IsrUsbd(void);
1293:+extern void IsrDma2(void);
1294:+
1295:+/************************* Timer ********************************/
1296:+static int intCount;
1297:+
1298:+void IsrWatchdog(void);
1299:+
1300:+void ClearPending(int bit)
1301:+{
1302:+ intregs->SRCPND = bit;
1303:+ intregs->INTPND = bit;
1304:+}
1305:+
1306:+void Timer_InitEx(void)
1307:+{
1308:+ intCount=0;
1309:+ intregs->SUBSRCPND = (1<<13);
1310:+ ClearPending(BIT_WDT_AC97/*BIT_WDT*/);
1311:+ intregs->INTMSK&=~(BIT_WDT_AC97 /*BIT_WDT*/);
1312:+ intregs->INTSUBMSK &= ~(1<<13);
1313:+}
1314:+
1315:+
1316:+void Timer_StartEx(void)
1317:+{
1318:+ S3C24X0_WATCHDOG * const wdtregs = S3C24X0_GetBase_WATCHDOG();
1319:+
1320:+ wdtregs->WTCON=((get_PCLK()/1000000-1)<<8)|(0<<3)|(1<<2); // 16us
1321:+ wdtregs->WTDAT=0xffff;
1322:+ wdtregs->WTCNT=0xffff;
1323:+
1324:+ // 1/16/(65+1),interrupt enable,reset disable,watchdog enable
1325:+ wdtregs->WTCON=((get_PCLK()/1000000-1)<<8)|(0<<3)|(1<<2)|(0<<0)|(1<<5);
1326:+}
1327:+
1328:+unsigned int Timer_StopEx(void)
1329:+{
1330:+ int count;
1331:+ S3C24X0_WATCHDOG * const wdtregs = S3C24X0_GetBase_WATCHDOG();
1332:+
1333:+ wdtregs->WTCON=((get_PCLK()/1000000-1)<<8);
1334:+ intregs->INTMSK|=BIT_WDT_AC97; //BIT_WDT;
1335:+ intregs->INTSUBMSK |= (1<<13);
1336:+
1337:+ count=(0xffff-wdtregs->WTCNT)+(intCount*0xffff);
1338:+ return ((unsigned int)count*16/1000000);
1339:+}
1340:+
1341:+
1342:+void IsrWatchdog(void)
1343:+{
1344:+ intregs->SUBSRCPND = (1<<13);
1345:+ ClearPending(BIT_WDT_AC97 /* BIT_WDT */);
1346:+ intCount++;
1347:+}
1348:+
1349:+int g_TimerIntHappen;
1350:+void IsrTimer4(void)
1351:+{
1352:+ ClearPending(BIT_TIMER4);
1353:+ *(volatile int *)&g_TimerIntHappen = 1;
1354:+}
1355:+
1356:+
1357:+void Dummy_isr(void)
1358:+{
1359:+ printf("Dummy_isr error, interrupt number: %d, INTMSK = 0x%x/n", intregs->INTOFFSET, intregs->INTMSK);
1360:+ while(1);
1361:+}
1362:+
1363:+void Isr_Init(void)
1364:+{
1365:+ int i = 0;
1366:+ intregs = S3C24X0_GetBase_INTERRUPT();
1367:+
1368:+ for (i = 0; i < sizeof(isr_handle_array) / sizeof(isr_handle_array[0]); i++ )
1369:+ {
1370:+ isr_handle_array[i] = Dummy_isr;
1371:+ }
1372:+
1373:+ intregs->INTMOD=0x0; // All=IRQ mode
1374:+ intregs->INTMSK=BIT_ALLMSK; // All interrupt is masked.
1375:+
1376:+ //pISR_URXD0=(unsigned)Uart0_RxInt;
1377:+ //rINTMSK=~(BIT_URXD0); //enable UART0 RX Default value=0xffffffff
1378:+
1379:+ isr_handle_array[ISR_TIMER4_OFT] = IsrTimer4;
1380:+ isr_handle_array[ISR_WDT_OFT] = IsrWatchdog;
1381:+
1382:+#ifdef CONFIG_USB_DEVICE
1383:+ isr_handle_array[ISR_USBD_OFT] = IsrUsbd;
1384:+ isr_handle_array[ISR_DMA2_OFT] = IsrDma2;
1385:+ ClearPending(BIT_DMA2);
1386:+ ClearPending(BIT_USBD);
1387:+#endif
1388:+}
1389:+
1390:+
1391:+void IRQ_Handle()
1392:+{
1393:+ unsigned long oft = intregs->INTOFFSET;
1394:+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
1395:+
1396:+// printk("IRQ_Handle: %d/n", oft);
1397:+
1398:+ //ÇåÖжÏ
1399:+ if( oft == 4 ) gpio->EINTPEND = 1<<7; //EINT4-7ºÏÓÃIRQ4£¬×¢ÒâEINTPEND[3:0]±£ÁôÎŽÓã¬ÏòÕâЩλЎÈë1¿ÉÄܵŒÖÂÎŽÖªœá¹û
1400:+ intregs->SRCPND = 1<<oft;
1401:+ intregs->INTPND = intregs->INTPND;
1402:+
1403:+ /* run the isr */
1404:+ isr_handle_array[oft]();
1405:+}
1406:+
1407:+/* End : add by www.embedsky.net */
1408:+
1409: #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
1410:diff -Nurw sanEmbeded/u-boot-1.1.6/cpu/arm920t/s3c24x0/Makefile EmbedSky/u-boot-1.1.6/cpu/arm920t/s3c24x0/Makefile
1411:--- sanEmbeded/u-boot-1.1.6/cpu/arm920t/s3c24x0/Makefile 2006-11-02 22:15:01.000000000 +0800
1412:+++ EmbedSky/u-boot-1.1.6/cpu/arm920t/s3c24x0/Makefile 2007-09-15 00:27:56.000000000 +0800
1413:@@ -26,7 +26,7 @@
1414: LIB = $(obj)lib$(SOC).a
1415:
1416: COBJS = i2c.o interrupts.o serial.o speed.o /
1417:- usb_ohci.o
1418:+ usb_ohci.o nand_flash.o
1419:
1420: SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1421: OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
1422:diff -Nurw sanEmbeded/u-boot-1.1.6/cpu/arm920t/s3c24x0/nand_flash.c EmbedSky/u-boot-1.1.6/cpu/arm920t/s3c24x0/nand_flash.c
1423:--- sanEmbeded/u-boot-1.1.6/cpu/arm920t/s3c24x0/nand_flash.c 1970-01-01 08:00:00.000000000 +0800
1424:+++ EmbedSky/u-boot-1.1.6/cpu/arm920t/s3c24x0/nand_flash.c 2008-07-14 22:19:12.000000000 +0800
1425:@@ -0,0 +1,186 @@
1426:+/*
1427:+ * Nand flash interface of s3c2410/s3c2440, by www.embedsky.net
1428:+ * Changed from drivers/mtd/nand/s3c2410.c of kernel 2.6.13
1429:+ */
1430:+
1431:+#include <common.h>
1432:+
1433:+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
1434:+#include <s3c2410.h>
1435:+#include <nand.h>
1436:+
1437:+DECLARE_GLOBAL_DATA_PTR;
1438:+
1439:+#define S3C2410_NFSTAT_READY (1<<0)
1440:+#define S3C2410_NFCONF_nFCE (1<<11)
1441:+
1442:+#define S3C2440_NFSTAT_READY (1<<0)
1443:+#define S3C2440_NFCONT_nFCE (1<<1)
1444:+
1445:+
1446:+/* select chip, for s3c2410 */
1447:+static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
1448:+{
1449:+ S3C2410_NAND * const s3c2410nand = S3C2410_GetBase_NAND();
1450:+
1451:+ if (chip == -1) {
1452:+ s3c2410nand->NFCONF |= S3C2410_NFCONF_nFCE;
1453:+ } else {
1454:+ s3c2410nand->NFCONF &= ~S3C2410_NFCONF_nFCE;
1455:+ }
1456:+}
1457:+
1458:+/* command and control functions, for s3c2410
1459:+ *
1460:+ * Note, these all use tglx's method of changing the IO_ADDR_W field
1461:+ * to make the code simpler, and use the nand layer's code to issue the
1462:+ * command and address sequences via the proper IO ports.
1463:+ *
1464:+*/
1465:+static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd)
1466:+{
1467:+ S3C2410_NAND * const s3c2410nand = S3C2410_GetBase_NAND();
1468:+ struct nand_chip *chip = mtd->priv;
1469:+
1470:+ switch (cmd) {
1471:+ case NAND_CTL_SETNCE:
1472:+ case NAND_CTL_CLRNCE:
1473:+ printf("%s: called for NCE/n", __FUNCTION__);
1474:+ break;
1475:+
1476:+ case NAND_CTL_SETCLE:
1477:+ chip->IO_ADDR_W = (void *)&s3c2410nand->NFCMD;
1478:+ break;
1479:+
1480:+ case NAND_CTL_SETALE:
1481:+ chip->IO_ADDR_W = (void *)&s3c2410nand->NFADDR;
1482:+ break;
1483:+
1484:+ /* NAND_CTL_CLRCLE: */
1485:+ /* NAND_CTL_CLRALE: */
1486:+ default:
1487:+ chip->IO_ADDR_W = (void *)&s3c2410nand->NFDATA;
1488:+ break;
1489:+ }
1490:+}
1491:+
1492:+/* s3c2410_nand_devready()
1493:+ *
1494:+ * returns 0 if the nand is busy, 1 if it is ready
1495:+ */
1496:+static int s3c2410_nand_devready(struct mtd_info *mtd)
1497:+{
1498:+ S3C2410_NAND * const s3c2410nand = S3C2410_GetBase_NAND();
1499:+
1500:+ return (s3c2410nand->NFSTAT & S3C2410_NFSTAT_READY);
1501:+}
1502:+
1503:+
1504:+/* select chip, for s3c2440 */
1505:+static void s3c2440_nand_select_chip(struct mtd_info *mtd, int chip)
1506:+{
1507:+ S3C2440_NAND * const s3c2440nand = S3C2440_GetBase_NAND();
1508:+
1509:+ if (chip == -1) {
1510:+ s3c2440nand->NFCONT |= S3C2440_NFCONT_nFCE;
1511:+ } else {
1512:+ s3c2440nand->NFCONT &= ~S3C2440_NFCONT_nFCE;
1513:+ }
1514:+}
1515:+
1516:+/* command and control functions */
1517:+static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd)
1518:+{
1519:+ S3C2440_NAND * const s3c2440nand = S3C2440_GetBase_NAND();
1520:+ struct nand_chip *chip = mtd->priv;
1521:+
1522:+ switch (cmd) {
1523:+ case NAND_CTL_SETNCE:
1524:+ case NAND_CTL_CLRNCE:
1525:+ printf("%s: called for NCE/n", __FUNCTION__);
1526:+ break;
1527:+
1528:+ case NAND_CTL_SETCLE:
1529:+ chip->IO_ADDR_W = (void *)&s3c2440nand->NFCMD;
1530:+ break;
1531:+
1532:+ case NAND_CTL_SETALE:
1533:+ chip->IO_ADDR_W = (void *)&s3c2440nand->NFADDR;
1534:+ break;
1535:+
1536:+ /* NAND_CTL_CLRCLE: */
1537:+ /* NAND_CTL_CLRALE: */
1538:+ default:
1539:+ chip->IO_ADDR_W = (void *)&s3c2440nand->NFDATA;
1540:+ break;
1541:+ }
1542:+}
1543:+
1544:+/* s3c2440_nand_devready()
1545:+ *
1546:+ * returns 0 if the nand is busy, 1 if it is ready
1547:+ */
1548:+static int s3c2440_nand_devready(struct mtd_info *mtd)
1549:+{
1550:+ S3C2440_NAND * const s3c2440nand = S3C2440_GetBase_NAND();
1551:+
1552:+ return (s3c2440nand->NFSTAT & S3C2440_NFSTAT_READY);
1553:+}
1554:+
1555:+/*
1556:+ * Nand flash hardware initialization:
1557:+ * Set the timing, enable NAND flash controller
1558:+ */
1559:+static void s3c24x0_nand_inithw(void)
1560:+{
1561:+ S3C2410_NAND * const s3c2410nand = S3C2410_GetBase_NAND();
1562:+ S3C2440_NAND * const s3c2440nand = S3C2440_GetBase_NAND();
1563:+
1564:+#define TACLS 0
1565:+#define TWRPH0 4
1566:+#define TWRPH1 2
1567:+
1568:+ if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
1569:+ {
1570:+ /* Enable NAND flash controller, Initialize ECC, enable chip select, Set flash memory timing */
1571:+ s3c2410nand->NFCONF = (1<<15)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0);
1572:+ }
1573:+ else
1574:+ {
1575:+ /* Set flash memory timing */
1576:+ s3c2440nand->NFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4);
1577:+ /* Initialize ECC, enable chip select, NAND flash controller enable */
1578:+ s3c2440nand->NFCONT = (1<<4)|(0<<1)|(1<<0);
1579:+ }
1580:+}
1581:+
1582:+/*
1583:+ * Called by drivers/nand/nand.c, initialize the interface of nand flash
1584:+ */
1585:+void board_nand_init(struct nand_chip *chip)
1586:+{
1587:+ S3C2410_NAND * const s3c2410nand = S3C2410_GetBase_NAND();
1588:+ S3C2440_NAND * const s3c2440nand = S3C2440_GetBase_NAND();
1589:+
1590:+ s3c24x0_nand_inithw();
1591:+
1592:+ if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410) {
1593:+ chip->IO_ADDR_R = (void *)&s3c2410nand->NFDATA;
1594:+ chip->IO_ADDR_W = (void *)&s3c2410nand->NFDATA;
1595:+ chip->hwcontrol = s3c2410_nand_hwcontrol;
1596:+ chip->dev_ready = s3c2410_nand_devready;
1597:+ chip->select_chip = s3c2410_nand_select_chip;
1598:+ chip->options = 0;
1599:+ } else {
1600:+ chip->IO_ADDR_R = (void *)&s3c2440nand->NFDATA;
1601:+ chip->IO_ADDR_W = (void *)&s3c2440nand->NFDATA;
1602:+ chip->hwcontrol = s3c2440_nand_hwcontrol;
1603:+ chip->dev_ready = s3c2440_nand_devready;
1604:+ chip->select_chip = s3c2440_nand_select_chip;
1605:+ chip->options = 0;
1606:+ }
1607:+
1608:+ chip->eccmode = NAND_ECC_SOFT;
1609:+}
1610:+
1611:+#endif
1612:diff -Nurw sanEmbeded/u-boot-1.1.6/cpu/arm920t/s3c24x0/serial.c EmbedSky/u-boot-1.1.6/cpu/arm920t/s3c24x0/serial.c
1613:--- sanEmbeded/u-boot-1.1.6/cpu/arm920t/s3c24x0/serial.c 2006-11-02 22:15:01.000000000 +0800
1614:+++ EmbedSky/u-boot-1.1.6/cpu/arm920t/s3c24x0/serial.c 2009-03-08 15:39:50.000000000 +0800
1615:@@ -180,4 +180,51 @@
1616: }
1617: }
1618:
1619:+#if 1 //HJ_add_start
1620:+int getc_errno = 0;
1621:+__u8 do_getc(unsigned long timeout, int *statp)
1622:+{
1623:+ __u8 c, rxstat;
1624:+ int do_timeout = timeout != 0;
1625:+ S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
1626:+
1627:+ getc_errno = 0; /* reste errno */
1628:+
1629:+ while(!(uart->UTRSTAT & 0x1)) {
1630:+
1631:+ if (do_timeout) {
1632:+ if (!timeout)
1633:+ break;
1634:+ timeout--;
1635:+ }
1636:+
1637:+ }
1638:+
1639:+ if (do_timeout && timeout == 0) {
1640:+ c = 0;
1641:+ rxstat = -1;
1642:+ } else {
1643:+ c = (uart->URXH & 0xff);
1644:+ rxstat = (uart->UERSTAT & 0xf);
1645:+ }
1646:+
1647:+ if (rxstat) {
1648:+ getc_errno = rxstat;
1649:+ if (statp)
1650:+ *statp = rxstat;
1651:+ }
1652:+ return (c);
1653:+}
1654:+/*
1655:+ * Reads and returns a character from the serial port
1656:+ * - Times out after delay iterations checking for presence of character
1657:+ * - Sets *error_p to UART error bits or - on timeout
1658:+ * - On timeout, sets *error_p to -1 and returns 0
1659:+ */
1660:+char awaitkey2(unsigned long delay, int* error_p)
1661:+{
1662:+ return (do_getc(delay, error_p));
1663:+}
1664:+#endif //HJ_add_end
1665:+
1666: #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
1667:diff -Nurw sanEmbeded/u-boot-1.1.6/cpu/arm920t/s3c24x0/speed.c EmbedSky/u-boot-1.1.6/cpu/arm920t/s3c24x0/speed.c
1668:--- sanEmbeded/u-boot-1.1.6/cpu/arm920t/s3c24x0/speed.c 2006-11-02 22:15:01.000000000 +0800
1669:+++ EmbedSky/u-boot-1.1.6/cpu/arm920t/s3c24x0/speed.c 2008-07-14 22:19:00.000000000 +0800
1670:@@ -38,6 +38,8 @@
1671: #include <s3c2410.h>
1672: #endif
1673:
1674:+DECLARE_GLOBAL_DATA_PTR;
1675:+
1676: #define MPLL 0
1677: #define UPLL 1
1678:
1679:@@ -67,7 +69,11 @@
1680: p = ((r & 0x003F0) >> 4) + 2;
1681: s = r & 0x3;
1682:
1683:+ /* support both of S3C2410 and S3C2440, by www.embedsky.net */
1684:+ if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
1685: return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
1686:+ else
1687:+ return((CONFIG_SYS_CLK_FREQ * m * 2) / (p << s)); /* S3C2440 */
1688: }
1689:
1690: /* return FCLK frequency */
1691:@@ -76,20 +82,99 @@
1692: return(get_PLLCLK(MPLL));
1693: }
1694:
1695:+/* for s3c2440 */
1696:+#define S3C2440_CLKDIVN_PDIVN (1<<0)
1697:+#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
1698:+#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
1699:+#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
1700:+#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
1701:+#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
1702:+#define S3C2440_CLKDIVN_UCLK (1<<3)
1703:+
1704:+#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
1705:+#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
1706:+#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
1707:+#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
1708:+#define S3C2440_CAMDIVN_DVSEN (1<<12)
1709:+
1710: /* return HCLK frequency */
1711: ulong get_HCLK(void)
1712: {
1713: S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1714:+ unsigned long clkdiv;
1715:+ unsigned long camdiv;
1716:+ int hdiv = 1;
1717:
1718:+ /* support both of S3C2410 and S3C2440, by www.embedsky.net */
1719:+ if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
1720: return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
1721:+ else
1722:+ {
1723:+ clkdiv = clk_power->CLKDIVN;
1724:+ camdiv = clk_power->CAMDIVN;
1725:+
1726:+ /* work out clock scalings */
1727:+
1728:+ switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
1729:+ case S3C2440_CLKDIVN_HDIVN_1:
1730:+ hdiv = 1;
1731:+ break;
1732:+
1733:+ case S3C2440_CLKDIVN_HDIVN_2:
1734:+ hdiv = 2;
1735:+ break;
1736:+
1737:+ case S3C2440_CLKDIVN_HDIVN_4_8:
1738:+ hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
1739:+ break;
1740:+
1741:+ case S3C2440_CLKDIVN_HDIVN_3_6:
1742:+ hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
1743:+ break;
1744:+ }
1745:+
1746:+ return get_FCLK() / hdiv;
1747:+ }
1748: }
1749:
1750: /* return PCLK frequency */
1751: ulong get_PCLK(void)
1752: {
1753: S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
1754:+ unsigned long clkdiv;
1755:+ unsigned long camdiv;
1756:+ int hdiv = 1;
1757:
1758:+ /* support both of S3C2410 and S3C2440, by www.embedsky.net */
1759:+ if (gd->bd->bi_arch_number == MACH_TYPE_SMDK2410)
1760: return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
1761:+ else
1762:+ {
1763:+ clkdiv = clk_power->CLKDIVN;
1764:+ camdiv = clk_power->CAMDIVN;
1765:+
1766:+ /* work out clock scalings */
1767:+
1768:+ switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
1769:+ case S3C2440_CLKDIVN_HDIVN_1:
1770:+ hdiv = 1;
1771:+ break;
1772:+
1773:+ case S3C2440_CLKDIVN_HDIVN_2:
1774:+ hdiv = 2;
1775:+ break;
1776:+
1777:+ case S3C2440_CLKDIVN_HDIVN_4_8:
1778:+ hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
1779:+ break;
1780:+
1781:+ case S3C2440_CLKDIVN_HDIVN_3_6:
1782:+ hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
1783:+ break;
1784:+ }
1785:+
1786:+ return get_FCLK() / hdiv / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
1787:+ }
1788: }
1789:
1790: /* return UCLK frequency */
1791:--- sanEmbeded/u-boot-1.1.6/lib_arm/board.c 2006-11-02 22:15:01.000000000 +0800
1792:+++ EmbedSky/u-boot-1.1.6/lib_arm/board.c 2009-08-07 14:10:58.000000000 +0800
1793:@@ -132,7 +132,7 @@
1794:
1795: static int display_banner (void)
1796: {
1797:- printf ("/n/n%s/n/n", version_string);
1798:+// printf ("/n/n%s/n/n", version_string); //HJ
1799: debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX/n",
1800: _armboot_start, _bss_start, _bss_end);
1801: #ifdef CONFIG_MODEM_SUPPORT
1802:@@ -170,8 +170,8 @@
1803: for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
1804: size += gd->bd->bi_dram[i].size;
1805: }
1806:- puts("DRAM: ");
1807:- print_size(size, "/n");
1808:+// puts("DRAM: "); //HJ
1809:+// print_size(size, "/n"); //HJ
1810: #endif
1811:
1812: return (0);
1813:@@ -180,8 +180,8 @@
1814: #ifndef CFG_NO_FLASH
1815: static void display_flash_config (ulong size)
1816: {
1817:- puts ("Flash: ");
1818:- print_size (size, "/n");
1819:+// puts ("Flash: "); //HJ
1820:+// print_size (size, "/n"); //HJ
1821: }
1822: #endif /* CFG_NO_FLASH */
1823:
1824:@@ -297,7 +297,7 @@
1825: mem_malloc_init (_armboot_start - CFG_MALLOC_LEN);
1826:
1827: #if (CONFIG_COMMANDS & CFG_CMD_NAND)
1828:- puts ("NAND: ");
1829:+// puts ("NAND: "); //HJ
1830: nand_init(); /* go init the NAND */
1831: #endif
1832:
1833:@@ -363,6 +363,9 @@
1834: /* enable exceptions */
1835: enable_interrupts ();
1836:
1837:+ /* add by www.embedsky.net */
1838:+ usb_init();
1839:+
1840: /* Perform network card initialisation if necessary */
1841: #ifdef CONFIG_DRIVER_CS8900
1842: cs8900_get_enetaddr (gd->bd->bi_enetaddr);
1843:@@ -393,8 +396,10 @@
1844: #endif
1845: eth_initialize(gd->bd);
1846: #endif
1847:+
1848: /* main_loop() can return to retry autoboot, if so just run it again. */
1849:- for (;;) {
1850:+ for (;;)
1851:+ {
1852: main_loop ();
1853: }
1854: