TMS320C6713与TMS320C6713B区别

TMS320C6713B是TMS320C6713的升级版本，将Silicon Revision升级到了2.0，两者的区别在“spra851h”的文档中有注明参见链接：http://www.ti.com/lit/an/spra851h/spra851h.pdf

 

文档第八页相关说明如下：

2.1 C6713B Versus C6713 New Features [D]
In addition to the new/enhanced peripherals listed in section 1.12, the C6713B DSP features
new enhancements over the C6713 device. These features are compatible with existing C6713
designs.
• P-bit in Cache Configuration (CCFG) register
The C6713B device includes an enhancement to the cache configuration (CCFG) register. A
”P” bit (CCFG.31) allows the programmer to select the priority of accesses to L2 memory
originating from the transfer crossbar (TC) over accesses originating from the L1D memory
system. While the EDMA normally has no issue accessing L2 memory due to the high hit
rates on the L1D memory system, there are pathological cases where certain CPU behavior
could block the EDMA from accessing the L2 memory for long enough to cause a missed
deadline when transferring data to a peripheral such as the McASP or McBSP. This can be
avoided by setting the P bit to ”1” because the EDMA will assume a higher priority than the
L1D memory system when accessing L2 memory. For more details on this feature, see the
TMS320C6713, TMS320C6713B Floating-Point Digital Signal Processor data sheet
(SPRS186) and the TMS320C6713, TMS320C6713B Digital Signal Processor Silicon Errata
(Silicon Revision 2.0, 1.1) (SPRZ191).
• EMIF Big Endian correctness
The C6713B device allows the flexibility to change the EMIF data placement on the EMIF
bus. When using the default setting of pin HD12 (pulled high) for the C6713B, the EMIF will
present 8-bit or 16-bit data on the ED[7:0] side of the bus if using Little Endian mode and to
the ED[31:24] side of the bus if using Big Endian mode. When pin HD12 is pulled low for the
C6713B, the EMIF will present 8-bit or 16-bit data on the ED[7:0] side of the bus, regardless
of the endianess. For more details on this enhancement, see the TMS320C6713,
TMS320C6713B Floating-Point Digital Signal Processor data sheet (SPRS186).

 

如上所述，其实也就两处改动吧，6713B是6713的一个新版本吧，在TI的文档中，有专门的TMS320C6713B和TMS320C6713，也有二者混为一起的，在TMS320C6713B中的内核电压中提到了1.4V，这个不要大惊小怪，看一下1.4V后面是有备注的“GDP and ZDP packages C6711D-300 only”，其实6713B的文档是多个型号芯片的合一版，因些不要误解。

 

在硬件设计过程中，从6713迁移到6713B，要有如下改动：

1. 复位信号改动：6713B中去掉了内部上拉电阻，因此设计电路时注意加外部上拉或使用电压监控芯片

Possible system modifications include ac timing differences for McBSP (SPI mode and data
delay 0 mode only) and CLKOUT3, as well as the internal pull up resistor removal on the
C6713B \RESET pin. C6713B designs should incorporate either a voltage supervisor, which
drives when in the inactive state (\RESET = 1), or should include an external pull up resistor
on the \RESET pin.

2. CLKOUT3缓冲区不同：若要做硬件仿真需要使用C6713B IBIS模型

The CLKOUT3 buffer is different on the C6713B device. Systems migrating should use the
C6713B IBIS models to run board level signal simulations with the updated CLKOUT3 buffer
information